Sharif Digital Repository

A low-power technique to reduce the power consumption of the dynamic comparators is presented. Using this technique, the pre-ampli-fication phase of the comparator is stopped without any effect on the dynamic behaviour of the comparator. Therefore, the power consumption of the pre-amplifier stage which is the main part of the total power consumption is reduced significantly. Simulation results in various comparators reveal that the proposed technique reduces the total power consumption by more than 50%  

This paper presents a new low-power comparator-reduced hybrid ADC. The proposed ADC uses dynamic comparators to perform a high-speed low-power conversion. In order to reduce the offset and kickback noise effect of conventional dynamic comparators, a new low-kickback noise comparator with a high pre-amplifier gain is presented. Two 4bit and 8bit ADCs are designed and simulated in 0.18 μm CMOS technology with 1.8 v supply voltage. INL and DNL of 4bit ADC are less than 0.4LSB and 0.5LSB, respectively, while 8bit ADC obtains DNL and INL of 0.83LSB and 1.3LSB, respectively. With ENOB of 3.6bit and 7.2bit for 4bit and 8bit ADCs, the 4bit ADC consumes only 1.7 mW at the sampling rate of 400 Ms/s... 

This paper presents a new low-power reduced comparator flash ADC. The proposed ADC uses dynamic comparators to perform a high-speed low-power conversion. In order to reduce offset and kick-back noise effect of conventional dynamic comparators, a new comparator with a higher pre-amplifier gain along with the mathematical analysis is presented. The proposed 4bit ADC is simulated in 0.18um with 1.8-υ supply voltage. SNDR and SFDR of the ADC are 23dB and 26.5dB, respectively. The ADC consumes only 0.95mw at the sampling rate of 400MS/s. © 2017 IEEE  

In this paper, a low-power method for double-tail comparators is introduced. Using the proposed method, the power consumption of the pre-amplifier which is the dominant part is reduced considerably. Thanks to this method, the pre-amplifier is not able to draw more than required amount of power, therefore, the power is saved. Post layout and corner simulation results show the power consumption is reduced by about 40%. Moreover, several Monte-Carlo (M) simulations suggest the proposed method results in about 20% offset reduction at the cost of 5% area and 10% speed degradation. © 2019 Elsevier B.V  

A low power analog to digital converter (ADC), based on a pipelining method employed in successive approximation register (SAR) architecture is presented. This structure is a two-stage pipeline SAR ADC with asymmetrical time interleaved (TI) channels, aimed to reach sampling rate as high as about threefold of a conventional SAR ADC while benefiting from its low power consumption and small area. Passive residue conversion without inter-stage amplifier and symphonic collaboration of stages are employed to design a low power, high speed, and accurate converter. In the proposed architecture, every signal sample experiences equal comparator offset during its conversion due to the applied novel... 

In this paper, a method is presented to reduce the power consumption of the two-stage dynamic comparators. In the two-stage dynamic comparators, the first stage (pre-amplifier stage) amplifies the input differential voltage. Then the second stage (latch stage) is activated and finishes the comparison. When the comparison is about to finish, the balance of the positive feedback of the latch stage tends to tilt toward one of the outputs; after this, to the end of the comparison, there is no need for additional pre-amplification gain which causes excess power consumption. In this paper, a method is proposed to eliminate this part of power consumption. It is shown that while reducing the power... 

A low-power comparator is presented. pMOS transistors are used at the input of the preamplifier of the comparator as well as the latch stage. Both stages are controlled by a special local clock generator. At the evaluation phase, the latch is activated with a delay to achieve enough preamplification gain and avoid excess power consumption. Meanwhile, small cross-coupled transistors increase the preamplifier gain and decrease the input common mode of the latch to strongly turn on the pMOS transistors (at the latch input) and reduce the delay. Unlike the conventional comparator, the proposed structure let us set the optimum delay for preamplification and avoid excess power consumption. The... 

In double tail comparators, the pre-amplifier amplifies the input differential voltage and when the output Vcm of the pre-amplifier becomes larger than Vth of the latch input transistors, the latch is activated and finalizes the comparison. As a result, the pre-amplification delay is fixed to a value and cannot be set at the minimum required delay, to save power and improve offset. In fact, when the latch is activated the pre-amplifier output differential voltage is still growing but the latch finishes the comparison before the maximum differential gain is formed and applied to the latch. In this paper, a comparator is proposed in which the preamplifier is turned off when the maximum gain is... 

A charge sharing technique for high-speed double-tail comparators is presented. This technique is applied to the pre-amplifier stage of the dynamic comparators so that the maximum differential gain is applied to the latch during the latching process reducing the input referred offset voltage. In dynamic comparators a large portion of the input referred offset voltage is coming from the latch, and the proposed technique is introduced to alleviate this issue. Monte- Carlo simulations show that the proposed technique reduces the offset voltage from 16 mV to 8 mV. Due to the charge sharing technique, the pre-amplifier draws just enough power for its operation reducing the average power by 40%... 

A low-power high-speed two-stage dynamic comparator is presented. In this circuit, PMOS transistors are used at the input of the first and second stages of the comparator. At the evaluation phase, the second stage is activated after the first stage with a predetermined delay to achieve a controllable pre-amplifier gain. Also, the first stage is turned off after the delay to reduce overall power consumption. Simulation results in 0.18 μτη CMOS technology, prove that the proposed circuit reduces the power consumption by a factor of two and reduces comparison time as large as 210ps in the same budget of offset voltage compared to the conventional circuit. Moreover, the offset voltage and power... 

A low-power high-speed two-stage dynamic comparator is presented. In this circuit, the voltage swing of the first stage of the comparator, pre-amplifier stage, is limited to Vdd/2 in order to reduce the first stage power consumption. Also, this voltage swing limitation provides a strong drive at the evaluation phase for the second stage to enhance the comparison speed. Analytical derivations along with post layout simulation results prove that the proposed method speeds up the conventional circuit by a factor of two in the same budget of power consumption and offset voltage. Furthermore, the proposed circuit offers a wide input common mode range as large as the supply voltage while employing... 

A low power four bit mixed Successive Approximation Register (SAR)-Flash Analog to Digital Converter (ADC) for Sigma-Delta ADC applications is presented. The ADC uses three comparators in order to reduce the latency of typical SAR ADCs. Three comparators are used for conversion of 2 bits per one clock cycle. One of the Digital to Analog Converters (DACs) is replaced by three resistors which can save power and area. The ADC is simulated by Cadence Spectre using TSMC 0.18um COMS technology. The power consumption at 165MS/s and 1.8V supply voltage is 1.8mW. The SNDR and SFDR for 10MHz input are 19.8dB and 28.4dB, respectively  

A low-power high-speed two-stage dynamic comparator is presented. The voltage fluctuation at the first stage of the comparator (pre-Amplifier stage) is limited to V dd=2. Therefore, the power consumption of the first stage which is the dominant part of the total power consumption is reduced. The output voltage of the first stage is kept above V dd=2. As a result, during the comparison the second stage of the comparator (latch) is activated stronger compared to the conventional comparator. To prove the benefits of the proposed comparator, the proposed and the other circuits are simulated in the equal budget of power and offset. Simulation results prove that the proposed comparator is faster... 

A novel structure of Capacitive Digital to Analog Converters (CDAC) for Successive Approximation Register Analog to Digital Converters (SAR ADC) is presented. In this CDAC, a number of pre-charged capacitors are placed in different series configurations to produce a desired voltage level. Therefore, given an input code, a series configuration of the capacitors is created to produce a voltage. Current is drawn from the supply voltage only in one step of the ADC conversion to reduce the power consumption. Therefore, the proposed CDAC consumes a fixed and small amount of power regardless of the input code. The output common mode voltage (Vcm) of the DAC remains fixed for all the digital codes.... 

A low-power technique for high-resolution comparators is introduced. In this technique, p-type metal-oxide-semiconductor field-effect transistors are employed as the input of the latch of the comparator just like the input of the preamplifier. The latch and preamplifier stages are activated in a special pattern using an inverter-based controller. Unlike the conventional comparator, the preamplification delay can be set to an optimum low value even if after the preamplification, the output voltages is less than n-channel metal-oxide semiconductor voltage threshold. As a result, the proposed comparator reduces the power consumption significantly and enhances the speed. The speed and power...