Sharif Digital Repository

In this study, the performance of virtual cut-through switching in the cube-based OTIS architecture, an optoelectronic interconnection architecture for multicomputer systems, is empirically analyzed. Deadlock-free deterministic and adaptive minimal path routing algorithms for this architecture are introduced, and the effects of different network and traffic parameters on average message latency are investigated. This analysis presents a relatively more realistic view of the OTIS architecture than that presented in previous work by considering issues related to a lower level of abstraction (the routing and switching of messages). Among other results, the analysis indicates that depending on... 

Future communication and computation devices require mechanisms for on-the-fly reconfiguration in their protocol stack to operate in different situations and networks. This paper proposes a component-based framework for dynamic-reconfigurable protocol stack. Considering that every running protocol component communicates with at least one peer component, unlike related work our framework supports synchronous reconfiguration of two peer protocol components in two communicating protocol stacks. © Springer-Verlag Berlin Heidelberg 2007  

Semantic web search engines are evolving and many prototype systems and some implementation have been developed. However, there are some different views on what a semantic search engine should do. In this paper, a categorization scheme for semantic web search engines are introduced and elaborated. For each category, its components are described according to a proposed general architecture and various approaches employed in these components are discussed. We also propose some factors to evaluate systems in each category. © 2006 IEEE  

In an introductory course of computer architecture, it is of high value that students use a simple and special CPU designed for this purpose and also its graphical simulator for better understanding of the computer hardware operation. In this paper, we present Abu-Reiahn, a simple 8-bit processor which we have specifically designed and built as the introduction part of computer architecture course to help students familiarize with hardware and software of a real CPU. Effective use of our computer graphical simulator along with the hardware allow the students to deepen their knowledge of logic circuits and the need for desired timing signals in a CPU to perform specific tasks  

In this paper, we propose a low power register file architecture for embedded processors. The proposed architecture, "Value-Aware Partitioned Register File (VAP-RF)", employs a partitioning technique that divides the register file into two partitions such that the most frequently accessed registers are stored in the smaller register partition. In our partitioning algorithm, we introduce an aggressive clock-gating scheme based on narrow-value registers to furthermore reduce power. Experimental results on an ARM processor for selected MiBench workloads show that the proposed architecture has an average power saving of 70% over generic register file structure  

This paper presents a Data Width-aware Register file Protection (DWRP) technique to cope with Multiple Bit Upsets (MBUs) occurring in the register file of embedded processors. The DWRP technique has been proposed based on the fact that there are often a significant number of bits in the register file, which are not fully occupied by data. The DWRP technique efficiently exploits these available free bits for reliability enhancement purposes. In this regard, every register is equipped with three extra tag bits to specify the amount of available free bits in a register. Then the appropriate parity or hamming code is used based on the information of the tag field to protect the register file... 

In ubiquitous computing environments, many devices and agents interoperate with each other and use services provided by others. But the problem is that there may be requests that can not be fulfilled by available services. A solution to this problem is to use service brokers that compose existing services and create new value added services that can fulfill the clients' requests. In this paper, we present an architecture for a context-aware service broker that not only is able to compose services for responding to new requests, but also considers the context of its clients for providing customized and personalized outputs and behaviors. © 2006 IEEE  

Caches, which are comprised much of a CPU chip area and transistor counts, are reasonable targets for transient single and multiple faults induced from energetic particles. This paper presents: (1) a new fault detection scheme for tag arrays of cache memories and (2) an architectural cache to improve performance as well as dependability. In this architecture, cache space is divided into sets of different sizes and different tag lengths. Using the proposed fault detection scheme, i.e., GParity, when single and multiple errors are detected in a word, the word is rewritten by its correct data from memory and its GParity code is recomputed. The error detection scheme and the cache architecture... 

This paper presents a new cache scheme based on varying the size of sets in the set-associative cache hierarchically. In this scheme, all sets at a hierarchical level have same size but are fc times more than the size of sets in the next level of hierarchy where k is called division factor. Therefore the size of tag fields associated to each set is variable and it depends on the hierarchy level of the set it is in. This scheme is proposed to achieve higher hit ratios with respect to the two conventional schemes namely set-associative and direct mapping. The proposed scheme has been simulated with several standard trace files SPEC 2000 and statistics are gathered and analyzed for different... 

Software architectures and architectural styles are increasingly used for designing large-scale software systems. Alfa is a framework for the composition of style-based software architectures from a small set of primitives. It models the behavior of architectural components and connectors as orderings among events at their inputs and outputs. Formalizing such behavior is useful for checking conformance of architectures to their styles. We therefore propose a formal approach that uses data-abstract constraint automata to model the behavior of Alfa's compositions, and to verify their behavioral style conformance. We have also developed an automated conformance analyzer for Alfa. © 2004 IEEE  

Due to the growing demand for large memories, using emerging technologies such as Phase Change Memories (PCM) are inevitable. PCM with appropriate scalability, power consumption and multiple bits per cell storage capability is a probable candidate for substituting DRAM. Although storing multiple bits per cell seems to be a rational response to large memory demands, there is a significant problem to achieve this goal. Resistance drift problem is an important reliability concern that is coupled to a multi-level cell PCM (MLC PCM) memory system. In this paper, we propose a memory system architecture that, by exploiting the benefits of compression, converts resistance drift prone blocks to drift... 

In this paper, we propose a reconfigurable NoC in which a customized topology for a given application can be implemented. In this NoC, the nodes are grouped into some clusters interconnected by a reconfigurable communication infrastructure. The nodes inside a cluster are connected by a fixed topology. From the traffic management perspective, this structure benefits from the interesting characteristics of the mesh topology (efficient handling of local traffic where each node communicates with its neighbors), while avoids its drawbacks (the lack of short paths between remotely located nodes). We then present a design flow that maps the frequently communicating tasks of a given application into... 

The Graphics Processing Unit (GPU) is the most promising candidate platform for faster rate of improvement in peak processing speed, low latency and high performance. The highly programmable and multithreaded nature of GPUs makes them a remarkable candidate for general purpose computing. However, supporting non-graphics computing on graphics processors requires addressing several architecture challenges. In this paper, we focus on improving performance by better hiding long waiting time to transfer data from the slow global memory. Thereupon study an effective light-overhead prefetching mechanism, which utilizes idle processing elements. Our results show that we can potentially improve... 

In this paper, we propose a reconfigurable NoC in which a customized topology for a given application can be implemented. In this NoC, the nodes are grouped into some clusters interconnected by a reconfigurable communication infrastructure. The nodes inside a cluster are connected by a fixed topology. From the traffic management perspective, this structure benefits from the interesting characteristics of the mesh topology (efficient handling of local traffic where each node communicates with its neighbors), while avoids its drawbacks (the lack of short paths between remotely located nodes). We then present a design flow that maps the frequently communicating tasks of a given application into... 

In nanometer-scale process technologies, the effects of process variations are observed in Multiprocessor System-on-Chips (MPSoC) in terms of variations in frequencies and leakage powers among the processors on the same chip as well as across different chips of the same design. Traditionally, worst-case values are assumed for these parameters and then a deterministic optimization technique is applied to the MPSoC application under design. We show that such worst-case-based approaches are not optimal with the increasing variation observed at system-level, and instead, statistical approaches should be employed. We consider the problem of simultaneously choosing MPSoC architecture and task... 

Given a simple polygon P in the plane, we present a parallel algorithm for computing the visibility polygon of an observer point q inside P. We use chain visibility concept and a bottom-up merge method for constructing the visibility polygon of point q. The algorithm is simple and mainly designed for GPU architectures, where it runs in O(logn) time using O(n) processors. This is the first work on designing a GPU-based parallel algorithm for the visibility problem. To the best of our knowledge, the presented algorithm is also the first suboptimal parallel algorithm for the visibility problem that can be implemented on existing parallel architectures. We evaluated a sample implementation of... 

Energy reduction in embedded processors is a must since most embedded systems run on batteries and processor energy reduction helps increase usage time before needing a recharge. Register files are among the most power consuming parts of a processor core. Register file power consumption mainly depends on its size (height as well as width), especially in newer technologies where leakage power is increasing. We provide a register file architecture that, depending on the application behavior, dynamically (i) adapts the width of individual registers, and (ii) puts partitions of temporarily unused registers into low-power mode, so as to save both static and dynamic power. We show that our scheme...