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    Fast co-verification of HDL models

    , Article Microelectronic Engineering ; Volume 84, Issue 2 , 2007 , Pages 218-228 ; 01679317 (ISSN) Asadi, G ; Miremadi, S. G ; Ejlali, A ; Sharif University of Technology
    2007
    Abstract
    This paper presents a method for functional verification of HDL models of digital circuits. The method is based on a co-operation between a simulator and an emulator and utilizes the advantages of both simulation-based and emulation-based verification to form a fast co-verification approach. This is done by verifying the intensive time-consuming part of the circuit in the emulator and the non-synthesizable part as well as the part of the circuit that needs intensive redesign process during the early steps of the design phase in the simulator. To demonstrate the co-verification approach, a tool was developed, which supports Verilog, VHDL, and mixed Verilog-VHDL models. Three benchmarks... 

    Fault injection in mixed-signal environment using behavioral fault modeling in Verilog-A

    , Article Proceedings of the IEEE International Workshop on Behavioral Modeling and Simulation, BMAS, 23 September 2010 through 24 September 2010, San Jose, CA ; September , 2010 , Pages 69-74 ; 21603804 (ISSN) ; 9781424489954 (ISBN) Ahmadian, S. N ; Miremadi, S. G ; Sharif University of Technology
    2010
    Abstract
    Fault injection methods have been used for analyzing dependability characteristics of systems for years. In this paper we propose a practical mixed-signal fault injection flow that is fast as well as accurate. We described three classes of most common faults: i) Single event transients, ii) Electro-Magnetic interference and iii) Power disturbance faults. Fault models are implemented directly into circuit's devices using behavioral fault description in Verilog-A language. As an example for dependability evaluation, some test circuits have been prepared and the results of fault injection on their designs have been reported  

    High-throughput stream categorization and intrusion detection on GPU

    , Article 8th ACM/IEEE International Conference on Formal Methods and Models for Codesign, MEMOCODE 2010, 26 July 2010 through 28 July 2010 ; August , 2010 , Pages 81-84 ; 9781424478859 (ISBN) Khabbazian, M. H ; Eslamiy, H ; Totoniy, E ; Khademy, A ; Sharif University of Technology
    Abstract
    We present a design and implementation of a high-throughput deep packet inspection performing both stream categorization and intrusion detection on GPU platform using CUDA. This implementation is capable of matching 64 ethernet packet streams against 25 given regular expressions at 524 Mb/s rate on a computer system with GeForce GTX 295 graphic card  

    Contribution of controller area networks controllers to masquerade failures

    , Article 11th Pacific Rim International Symposium on Dependable Computing, PRDC 2005, Changsha, Hunan, 12 December 2005 through 14 December 2005 ; Volume 2005 , 2005 , Pages 310-314 ; 0769524923 (ISBN); 9780769524924 (ISBN) Salmani, H ; Miremadi, S. G ; Sharif University of Technology
    2005
    Abstract
    This paper scrutinizes faults in a CAN controller that may result in masquerade failures, and suggests an even parity mechanism to detect them with minimum hardware overhead. To do this, a CAN controller is modeled by VHDL at behavioral level and is exploited to setup a CAN-based network composed of two nodes. A total of 5,500 faults are injected into essential parts of one of the controllers. The results show that about 3.44% of faults terminate in masquerade failures. The results, also, show that Register bank in the CAN controller are the most sensitive portions in which 92.10% of faults occurring in the Register bank result in masquerade failures. The even parity mechanism detects about... 

    Designing best effort networks-on-chip to meet hard latency constraints

    , Article Transactions on Embedded Computing Systems ; Vol. 12, issue 4 , June , 2013 ; ISSN: 15399087 Seiculescu, C ; Rahmati, D ; Murali, S ; Sarbazi-Azad, H ; Benini, L ; Micheli, G. D ; Sharif University of Technology
    Abstract
    Many classes of applications require Quality of Service (QoS) guarantees from the system interconnect. In Networks-on-Chip (NoC) QoS guarantees usually translate into bandwidth and latency constraints for the traffic flows and require hardware support in the NoC fabric and its interfaces. In this article we present a novel NoC synthesis framework to automatically build networks that meet hard latency constraints of end-to-end traffic streams without requiring specialized hardware for the network components. The hard latency constraints are met by carefully designing the NoC topology and selecting the appropriate routes for flow using lean best-effort network components. We perform... 

    Essential design considerations for wireless multi-channel photoplethysmography system

    , Article IFMBE Proceedings, 23 November 2008 through 27 November 2008, Antwerp ; Volume 22 , 2008 , Pages 1066-1069 ; 16800737 (ISSN); 9783540892076 (ISBN) Kadhim, A. Y ; Mohd Ali, M. A ; Zahedi, E ; Sharif University of Technology
    2008
    Abstract
    The developed wireless multi-channel PPG system comprises tiered communication subsystem with two sensor modules and a single base module. The sensor modules process the input signals simultaneously into 16-bit samples and wirelessly transfer them to base module using Bluetooth technology. In base module, the samples are combined using time division multiplexing into composite stream and serially forwarded to the host computer. The string buffer is implemented in the sensor module firmware to increase the transfer time, transfer samples in chunks and eliminate the wireless transmission latency. The wireless network is established between modules. The newly implemented firmware results in... 

    Top-down design of a low-power multi-channel 2.5-Gbit/s/channel gated oscillator clock-recovery circuit

    , Article Design, Automation and Test in Europe, DATE '05, Munich, 7 March 2005 through 11 March 2005 ; Volume I , 2005 , Pages 258-263 ; 15301591 (ISSN); 0769522882 (ISBN); 9780769522883 (ISBN) Muller, P ; Tajalli, A ; Atarodi, M ; Leblebici, Y ; Sharif University of Technology
    2005
    Abstract
    We present a complete top-down design of a low-power multi-channel clock recovery circuit based on gated current-controlled oscillators. The flow includes several tools and methods used to specify block constraints, to design and verify the topology down to the transistor level, as well as to achieve a power consumption as low as 5mW/Gbit/s. Statistical simulation is used to estimate the achievable bit error rate in presence of phase and frequency errors and to prove the feasibility of the concept. VHDL modeling provides extensive verification of the topology. Thermal noise modeling based on well-known concepts delivers design parameters for the device sizing and biasing. We present two... 

    A high video quality Multiple Description Coding scheme for lossy channels

    , Article Proceedings - IEEE International Conference on Multimedia and Expo, 11 July 2011 through 15 July 2011, Barcelona ; 2011 ; 19457871 (ISSN) ; 9781612843490 (ISBN) Kazemi, M ; Sadeghi, K ; Shirmohammadi, S ; Sharif University of Technology
    2011
    Abstract
    Multiple Description Coding (MDC) is a technique where multiple streams from a source are generated, each individually decodable and mutually refinable. In this paper, a new Mixed Layer MDC (MLMDC) scheme is presented which achieves a higher side quality compared to conventional MDCs. The improved side performance leads to higher average video quality at the receiver in lossy networks. For each DCT coefficient, we generate two coefficients: Base Coefficient (BC) and Enhancement Coefficient (EC) which are combined together. When all descriptions are available, they are decomposed and decoded to achieve high quality video. When one description is not available, we use estimation to extract as... 

    Designing the FPGA-based system for Triangle Phase space Mapping (TPSM) of heart rate variability (HRV) signal

    , Article 2015 38th International Conference on Telecommunications and Signal Processing, TSP 2015, 9 July 2015 through 11 July 2015 ; July , 2015 , Page(s): 1 - 4 ; 9781479984985 (ISBN) Rezaei, S ; Moharreri, S ; Ghorshi, A ; Molnar K ; Herencsar N ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2015
    Abstract
    There has been an increasing interest in telemonitoring thanks to the availability of new technologies for data transmission and processing with better performances and lower costs. In this paper, we try to develop and implement the HRV signal processing into a Field Programmable Gate Array (FPGA). The hardware implementing algorithm was developed in Verilog Hardware Description Language (HDL). In designed hardware, after defining the number of samples in the input, we extract and analyses the Triangular Phase Space Mapping (TPSM), a novel method for representation of heart rate. The performance of the system was tested using MATLAB and validated based on the input signals  

    Rate/distortion optimization in multiple description video coding

    , Article Signal Processing: Image Communication ; Volume 36 , August , 2015 , Pages 95-105 ; 09235965 (ISSN) Kazemi, M ; Haj Sadeghi, K ; Shirmohammadi, S ; Moallem, P ; Sharif University of Technology
    Elsevier  2015
    Abstract
    Abstract Multiple Description Coding (MDC) is a technique where multiple streams from a video source are generated, each individually decodable and mutually refinable. MDC is a promising solution to overcome packet loss in video transmission over noisy channels, particularly for real-time applications in which retransmission of lost information is not practical. The error resiliency feature of MDC is achieved at the cost of redundancy, and the required amount of redundancy for each frame depends on the packet loss ratio and also the importance of the frame in the sequence. Due to the error propagation in video transmission over lossy channels, reference frames of a Group of Pictures (GOP)... 

    An efficient SRAM-Based reconfigurable architecture for embedded processors

    , Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ; Volume 38, Issue 3 , 2019 , Pages 466-479 ; 02780070 (ISSN) Tamimi, S ; Ebrahimi, Z ; Khaleghi, B ; Asadi, H ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2019
    Abstract
    Nowadays, embedded processors are widely used in wide range of domains from low-power to safety-critical applications. By providing prominent features such as variant peripheral support and flexibility to partial or major design modifications, field-programmable gate arrays (FPGAs) are commonly used to implement either an entire embedded system or a hardware description language-based processor, known as soft-core processor. FPGA-based designs, however, suffer from high power consumption, large die area, and low performance that hinders common use of soft-core processors in low-power embedded systems. In this paper, we present an efficient reconfigurable architecture to implement soft-core... 

    A performance and power analysis of WK-recursive and mesh networks for network-on-chips

    , Article 24th International Conference on Computer Design 2006, ICCD, San Jose, CA, 1 October 2006 through 4 October 2006 ; 2006 , Pages 142-147 Rahmati, D ; Kiasari, A. E ; Hessabi, S ; Sarbazi Azad, H ; Sharif University of Technology
    2006
    Abstract
    Network-on-Chip (NoC) has been proposed as an attractive alternative to traditional dedicated wires to achieve high performance and modularity. Power efficiency is one of the most important concerns in NoC architecture design. The choice of network topology is important in designing a low-power and high-performance NoC. In this paper, we propose the use of the WK-recursive networks to be used as the underlying topology in NoC. We have implemented VHDL hardware model of mesh and WK-recursive topologies and measured the latency results using simulation with these implementation. We also propose a novel approach in high level power modeling based on latency for these topologies and show that... 

    A Fast Soft Decision Algorithm for Cooperative Spectrum Sensing

    , Article IEEE Transactions on Circuits and Systems II: Express Briefs ; Volume 68, Issue 1 , 2021 , Pages 241-245 ; 15497747 (ISSN) Golvaei, M ; Fakharzadeh, M ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2021
    Abstract
    Hidden Primary User problem caused by fading and shadowing severely affects the detection rate of the cognitive radio systems with a single spectrum sensor. Cooperative Spectrum Sensing has been introduced to tackle this problem by using the spatial diversity of spectrum sensors. It is shown that the use of soft decision algorithms in fusion center has a better performance than hard decision algorithms. The problem of soft decision based on sensor measurements perfectly matches the Machine Learning paradigm. In this brief, a novel fast soft decision algorithm is proposed based on Machine Learning theory for wideband Cooperative Spectrum Sensing, which finds a decision boundary to classify...