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Energy Efficient Concurrent Test of Switches and Links for Networks-On-Chip
, M.Sc. Thesis Sharif University of Technology ; Hessabi, Shahin (Supervisor)
Abstract
Nowadays by increasing the number of processing cores in system-on-chip, using networks-on-chip, as an optimized interconnection foundation for transferring data between processing cores is inevitable .Based on this, the necessity of designing and implementing an optimized structure for testing network-on-chip, considering various overheads such as power consumption, latency, bandwidth and area, becomes an important issue in designing network-on-chip. The purpose of this project is to design an optimized structure for testing routers and connecting links in network, which considers power consumption overhead, latency and area overhead on one hand, and fault coverage on the other hand....
A novel GA-based High-Level Synthesis technique to enhance RT-level concurrent testing
, Article 14th IEEE International On-Line Testing Symposium, IOLTS 2008, Rhodes, 7 July 2008 through 9 July 2008 ; 2008 , Pages 173-174 ; 9780769532646 (ISBN) ; Aminzadeh, S ; Safari, S ; Navabi, Z ; Sharif University of Technology
2008
Abstract
This paper presents an efficient High-Level Synthesis (HLS) approach to improve RT-Level concurrent testing. The proposed method used for both fault detection and fault location. At first the available resources are used in their dead intervals to test active resources for fault detection, and then some changes are applied to the RT-Level controller to locate the faults. The fault detection step is based on a genetic algorithm (GA) search technique. This genetic algorithm is applied to the design after high level synthesis process to explore the test map. The proposed method has been evaluated based on dependability enhancement and area/latency overhead imposed to different benchmarks after...