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Continuous-time/discrete-time (CT/DT) cascaded sigma-delta modulator for high resolution and wideband applications
, Article WMED 2010 - 8th IEEE Workshop on Microelectronics and Electron Devices, 16 April 2010 through 16 April 2010 ; April , 2010 , Pages 33-36 ; 9781424465750 (ISBN) ; Sadeghi, K. H ; Ay, S. U ; Sharif University of Technology
2010
Abstract
This paper reports transistor-level design of a new continuous-time (CT), discrete-time (DT) cascaded sigma delta modulator (SDM). The combination of a CT first stage and a DT second stage was utilized to realize a high speed, high resolution analog-to-digital converter (ADC). Power consumption of CT first stage is lowered by optimizing the gain coefficients of CT integrators in a feedforward topology. Moreover double sampling (CDS) was used in second stage integrators to further reduce power consumption. Proposed new SDM is simulated in 0.18μm CMOS technology and achieves 84dB dynamic range for a 10MHz signal bandwidth. Total analog power dissipation measured was 44mW