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control-flow-checking
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A Post-Processor for Control Flow Checking of Jump and Branch Instructions
, M.Sc. Thesis Sharif University of Technology ; Miremadi, Ghasem (Supervisor)
Abstract
Ever increasing use of embedded systems has made them an inevitable part of human life. In 2006, more than 76% of fabricated microprocessors were used in embedded systems. On the other hand, the most important applications for embedded systems are the safty-critical applications and failure in these systems can ba catastrophic. Nowadays, the probability of transient faults has been increasing 8% with coming of the new age of fabrications. So, dependability has been an important concern for the desginers. Control flow checking has been one of the most important ways of avoding failurs.in this thesis a software control flow checking method has been introduced. This mechanism is based on branch...
Error detection enhancement in PowerPC architecture-based embedded processors
, Article Journal of Electronic Testing: Theory and Applications (JETTA) ; Volume 24, Issue 1-3 , 2008 , Pages 21-33 ; 09238174 (ISSN) ; Farivar, R ; Miremadi, S. G ; Sharif University of Technology
2008
Abstract
This paper presents a behavior-based error detection technique called Control Flow Checking using Branch Trace Exceptions for PowerPC processors family (CFCBTE). This technique is based on the branch trace exception feature available in the PowerPC processors family for debugging purposes. This technique traces the target addresses of program branches at run-time and compares them with reference target addresses to detect possible violations caused by transient faults. The reference target addresses are derived by a preprocessor from the source program. To enhance the error detection coverage, three other mechanisms, i.e., Machine Check Exception, System Trap Instructions and Work Load Timer...
Including Facilities in an Embedded Processor for External Watchdog Processors
, M.Sc. Thesis Sharif University of Technology ; Miremadi, Ghassem (Supervisor)
Abstract
The wide range of embedded processors and their reliance on nano-scale technologyhave brought them serious concerns on reliability, power consumption, timeliness and cost. Therefore, theseconcernsmust be addressed at the design process withemploying minimum facilities.This thesis proposes a low-cost concurrent error detection method based on control flow checking suitable for embedded processors. Most of the previous control flow checking methods either do not consider the embedded processors concerns, or they are not applicable to processors with on-chip cache memories.The key idea behind the proposed control flow checking method is to embed specific hardware components in the IP core of an...
Control-flow checking using branch instructions
, Article 5th International Conference on Embedded and Ubiquitous Computing, EUC 2008, Shanghai, 17 December 2008 through 20 December 2008 ; Volume 1 , January , 2008 , Pages 66-72 ; 9780769534923 (ISBN) ; Miremadi, S. G ; Ejlali, A ; IEEE Computer Society Technical Committee on Scalable Computing ; Sharif University of Technology
2008
Abstract
This paper presents a hardware control-flow checking scheme for RISC processor-based systems. This Scheme combines two error detection mechanisms to provide high coverage. The first mechanism uses parity bits to detect faults occurring in the opcodes and in the target addresses of branch instructions which lead to erroneous branches. The second mechanism uses signature monitoring to detect errors occurring in the sequential instructions. The scheme is implemented using a watchdog processor for an VHDL model of the LEON2 processor. About 31800 simulation faults were injected into the LEON2 processor. The results show that the error detection coverage is about 99.5% with average detection...
A software-based concurrent error detection technique for powerPC processor-based embedded systems
, Article 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2005, Monterey, CA, 3 October 2005 through 5 October 2005 ; 2005 , Pages 266-274 ; 15505774 (ISSN) ; Farivar, R ; Miremadi, S. G ; Aitken R ; Ito H ; Metra C ; Park N ; Sharif University of Technology
2005
Abstract
This paper presents a behavior-based error detection technique called Control Flow Checking using Branch Trace Exceptions for PowerPC processors family (CFCBTE). This technique is based on the branch trace exception feature available in the PowerPC processors family for debugging purposes. This technique traces the target addresses of program branches at run-time and compares them with reference target addresses to detect possible violations caused by transient faults. The reference target addresses are derived by a preprocessor from the source program. The proposed technique is experimentally evaluated on a 32-bit PowerPC microcontroller using software implemented fault injection (SWIFI)....
CFCET: A hardware-based control flow checking technique in COTS processors using execution tracing
, Article Microelectronics Reliability ; Volume 46, Issue 5-6 , 2006 , Pages 959-972 ; 00262714 (ISSN) ; Miremadi, S. G ; Sharif University of Technology
2006
Abstract
This paper presents a behavioral-based error detection technique called control flow checking by execution tracing (CFCET) to increase concurrent error detection capabilities of commercial off-the-shelf (COTS) processors. This technique traces the program jumps graph (PJG) at run-time and compares it with the reference jumps graph to detect possible violations caused by transient faults. The reference graph is driven by a preprocessor from the source program. The idea behind the CFCET is based on using an external watchdog processor (WDP) and also the internal execution tracing feature available in COTS processors to monitor the addresses of taken branches in a program, externally. This is...
Low cost concurrent error detection for on-chip memory based embedded processors
, Article Proceedings - 2011 IFIP 9th International Conference on Embedded and Ubiquitous Computing, EUC 2011, 24 October 2011 through 26 October 2011 ; October , 2011 , Pages 114-119 ; 9780769545523 (ISBN) ; Farbeh, H ; Fazeli, M ; Miremadi, S. G ; Sharif University of Technology
Abstract
This paper proposes an efficient concurrent error detection method using control flow checking for embedded processors. The proposed method is based on the co-operation of two hardware modules: 1) an on-chip hardware component to detect branch instructions and generate signatures for the running program, and 2) an external watchdog processor to compare runtime signatures and branch addresses with the information extracted offline. The proposed method is implemented on an embedded processor core and is evaluated by a simulation based statistical fault injection approach where faults are injected into cache and main memory. Experimental results show that the proposed method detects more than...
Software-based control flow error detection and correction using branch triplication
, Article Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011, 13 July 2011 through 15 July 2011 ; July , 2011 , Pages 214-217 ; 9781457710551 (ISBN) ; Fazeli, M ; Rad, H. I ; Miremadi, S. G ; Sharif University of Technology
2011
Abstract
Ever Increasing use of commercial off-the-shelf (COTS) processors to reduce cost and time to market in embedded systems has brought significant challenges in error detection and recovery methods employing in such systems. This paper presents a software based control flow error detection and correction technique, so called branch TMR (BTMR), suitable for use in COTS-based embedded systems. In BTMR method, each branch instruction is triplicated and a software interrupt routine is invoked to check the correctness of the branch instruction. During the execution of a program, when a branch instruction is executed, it is compared with the second redundant branch in the interrupt routine. If a...
Feature specific control flow checking in COTS-based embedded systems
, Article Proceedings - 3rd International Conference on Dependability, DEPEND 2010, 18 July 2010 through 25 July 2010 ; July , 2010 , Pages 58-63 ; 9780769540900 (ISBN) ; Miremadi, S.G ; IARIA ; Sharif University of Technology
2010
Abstract
While the Control Flow Checking (CFC) methods are using the ordinary instruction set and general Arithmetic and Logic Unit (ALU) features to protect the programs against the transient faults, this paper presents a new kind of CFC method, called feature specific CFC. The idea behind this method is using a specific internal hardware in modern processors which provides the ability to monitor internal various parameters of the program. This method is a pure software method and the external hardware overhead is zero. Other overheads have been measured experimentally by executing the workloads on a Pentium system. The execution time overhead is between 42% and 67% and the program size overhead is...
A checkpointing technique for rollback error recovery in embedded systems
, Article 2006 International Conference on Microelectronics, ICM 2006, Dhahran, 16 December 2006 through 19 December 2006 ; 2006 , Pages 174-177 ; 1424407656 (ISBN); 9781424407651 (ISBN) ; Miremadi, S. G ; Fazeli, M ; Arabian Consulting Engineering Center; Saudi Binladin Group; Advanced Electronics Company; HEIP ; Sharif University of Technology
2006
Abstract
In this paper, a general Checkpointing technique for rollback error recovery for embedded systems is proposed and evaluated. This technique is independent of used processor and employs the most important feature in control flow error detection mechanisms to simplify checkpoint selection and to minimize the overall code overhead. In this way, during the implementation of a control flow checking mechanism, the checkpoints are added to the program. To evaluate the Checkpointing technique, a pre-processor is implemented that selects and adds the checkpoints to three workload programs running in an 8051 microcontroller -based system. The evaluation is based on 3000 experiments for each...
Experimental evaluation of three concurrent error detection mechanisms
, Article 2006 International Conference on Microelectronics, ICM 2006, Dhahran, 16 December 2006 through 19 December 2006 ; 2006 , Pages 67-70 ; 1424407656 (ISBN); 9781424407651 (ISBN) ; Fazeli, M ; Miremadi, S. G ; Sharif University of Technology
2006
Abstract
This paper presents an experimental evaluation of the effectiveness of three hardware-based control flow checking mechanisms, using software-implemented fault injection (SWIFI) method. The fault detection technique uses reconfigurable of the shelf FPGAs to concurrently check the execution flow of the target program. The technique assigns signatures to the target program in the compile time and verifies the signatures using a FPGA as a watchdog processor to detect possible violation caused by the transient faults. A total of 3000 faults were injected in the experimental embedded system, which is based on an 8051 microcontroller, to measure the error detection coverage. The experimental...