Sharif Digital Repository

The most challenging issue of conventional Time Amplifiers (TAs) is their limited Dynamic Range (DR). This paper presents a mathematical analysis to clarify principle of operation of conventional 2× TA's. The mathematical derivations release strength reduction of the current sources of the TA is the simplest way to increase DR. Besides, a new technique is presented to expand the Dynamic Range (DR) of conventional 2× TAs. Proposed technique employs current subtraction in place of changing strength of current sources using conventional gain compensation methods, which results in more stable gain over a wider DR. The TA is simulated using Spectre-rf in TSMC 0.18um COMS technology. DR of the 2×... 

This study proposes a new fault detection method for modular multilevel converter (MMC) semiconductor power switches. While in common MMCs, the cells capacitor voltages are measured directly for control purposes, in this study voltage measurement point changes to the cell output terminal improving fault diagnosis ability. Based on this measurement reconfiguration, a novel fault detection algorithm is designed for MMCs semiconductor power switches. The open circuit and short circuit faults are detected based on unconformity between modules output voltage and switching signals. Simulation and experimental results confirm accurate and fast operation of the proposed method in faulty cell... 

In this paper, an FPGA-based fault-tolerant back-to-back converter without redundancy is studied. Before fault occurrence, the fault-tolerant converter operates like a conventional back-to-back six-leg converter, and after the fault, it becomes a five-leg converter. Design, implementation, and experimental verification of an FPGA-based reconfigurable control strategy for this converter are discussed. This reconfigurable control strategy allows the continuous operation of the converter with minimum affection from a fault in one of the semiconductor switches. A very fast detection scheme is used to detect and locate the fault. Implementation of the fault detection and of the fully digital... 

In this paper, an FPGA-controlled fault tolerant back-to-back converter for DFIG-based wind energy conversion application is studied. Before an open-circuit failure in one of the semiconductors, the fault tolerant converter operates as a conventional back-to-back six-leg one. After the fault occurrence in one of the switches, the converter will continue its operation with the remaining five healthy legs. Design, implementation, simulation and experimental verification of a reconfigurable control strategy for the fault tolerant six/five leg converter used in wind energy conversion are discussed. The proposed reconfigurable control strategy allows the uninterrupted operation of the converter... 

Plug-in hybrid electric vehicles draw electricity from the electrical grid and store energy in their batteries. To increase charge availability for plug-in hybrid electric vehicles, on-board chargers can be used, which should be small in size and lightweight. In this article, an on-board bidirectional soft-switched battery charger is proposed that utilizes a phase-shift-controlled dual-bridge series resonant converter with isolation. The bidirectional characteristic of proposed charger makes it suitable for vehicle-to-grid operation (i.e., injecting power from the vehicle to the grid) in smart grids. A switching control scheme is also proposed to provide soft-switching operation for all... 

A low power four bit mixed Successive Approximation Register (SAR)-Flash Analog to Digital Converter (ADC) for Sigma-Delta ADC applications is presented. The ADC uses three comparators in order to reduce the latency of typical SAR ADCs. Three comparators are used for conversion of 2 bits per one clock cycle. One of the Digital to Analog Converters (DACs) is replaced by three resistors which can save power and area. The ADC is simulated by Cadence Spectre using TSMC 0.18um COMS technology. The power consumption at 165MS/s and 1.8V supply voltage is 1.8mW. The SNDR and SFDR for 10MHz input are 19.8dB and 28.4dB, respectively  

Fast fault detection and converter reconfiguration is necessary for fault tolerant doubly fed induction generator (DFIG) in wind energy conversion systems (WECS) to prevent further damage and to make possible the continuity of service. Extra sensors are needed in order to detect the faults rapidly. In this paper, a very fast FPGA-based fault detection scheme is presented that minimizes the number of additional voltage sensors. A fault tolerant converter topology for this application is studied. Control and fault detection system are implemented on a single FPGA and Hardware in the Loop experiments are performed to evaluate the proposed detection scheme, the digital controller and the fault...