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A low power 1.2 GS/s 4-bit flash ADC in 0.18 μm CMOS
, Article Proceedings of IEEE East-West Design and Test Symposium, EWDTS 2013 ; 2013 ; 9781479920969 (ISBN) ; Sharifkhani, M ; Sadughi, S ; Sharif University of Technology
2013
Abstract
A low power 4-bit flash ADC is proposed. A new power reduction technique is employed which deactivates the unused blocks in the converter structure in order to reduce the power consumption. A new method for built-in threshold voltage generation together with a new offset calibration method is used to further reduce the power consumption in the converter. Monte-Carlo simulation shows that after calibration both the INL and the DNL are lower than 0.35 LSB. The converter achieves 3.5 effective number of bits (ENOB) at 1.2 GS/s sampling rate after the offset calibration is performed. It consumes 10 mW from a 1.8 V supply, yielding a FoM of 560 fJ/conversion.step in a 0.18 μm standard CMOS...
A Multi-Output high voltage dc power supply with fast regenerative rectifier
, Article 26th Iranian Conference on Electrical Engineering, ICEE 2018, 8 May 2018 through 10 May 2018 ; 2018 , Pages 1264-1268 ; 9781538649169 (ISBN) ; Kaboli, S ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2018
Abstract
A major problem in a multiple output converter structure is the different power flow via its various outputs. This problem leads to unwanted input DC-link voltage. This paper studies full bridge based DC-DC converters with multiple outputs. The effect of power flow variation is studied and a regenerative converter topology which controls the DC-link voltage by space voltage vector modulation technique is proposed. The proposed converter has a fast response to control the DC-link voltage in an acceptable band. Simulation and experimental results are presented to verify the analytical studies. © 2018 IEEE