Search for: critical-path-analysis
Article 8th International Symposium on Quality Electronic Design, ISQED 2007, San Jose, CA, 26 March 2007 through 28 March 2007 ; 2007 , Pages 380-385 ; 0769527957 (ISBN); 9780769527956 (ISBN) ; Miremadi, S. G ; Pradhan, D. K ; Mathew, J ; Sharif University of Technology
In this paper, we propose a new SEU-mitigative placement and routing of circuits in the FPGAs which is based on the popular VPR tool. The VPR tool is modified so that during placement and routing, decisions are taken with awareness of SEU-mitigation. Moreover, no redundancies during the placement and routing are used but the algorithms are based on the SEU avoidance. Using the modified tool, i.e., S-VPR, the role of placement and routing algorithms on the fault-tolerance of circuits implemented on FPGAs is achieved. The secondary propose of this paper is to find which of placement or routing is more suited for decreasing SEU sensibility of circuits and to find whether these SEU sensibility...
Article Scientia Iranica ; Volume 19, Issue 3 , 2012 , Pages 841-848 ; 10263098 (ISSN) ; Fatemi Ghomi, S. M. T ; Modarres, M ; Sharif University of Technology
In this paper, we develop an approach to optimally allocate a limited nonrenewable resource among the activities of a project, represented by a PERT-Type Network (PTN). The project needs to be completed within some specified due date. The objective is to maximize the probability of project completion on time. The duration of each activity is an arbitrary discrete random variable and also depends on the amount of consumable resource allocated to it. On the basis of the structure of networks, they are categorized as either reducible or irreducible. For each network structure, an analytical algorithm is presented. Through some examples, the algorithms are illustrated