Loading...
Search for: critical-path-delays
0.006 seconds

    Towards dark silicon era in FPGAs using complementary hard logic design

    , Article Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014 ; Sept , 2014 , pp. 1 - 6 ; ISBN: 9783000446450 Ahari, A ; Khaleghi, B ; Ebrahimi, Z ; Asadi, H ; Tahoori, M. B ; Sharif University of Technology
    Abstract
    While the transistor density continues to grow exponentially in Field-Programmable Gate Arrays (FPGAs), the increased leakage current of CMOS transistors act as a power wall for the aggressive integration of transistors in a single die. One recently trend to alleviate the power wall in FPGAs is to turn off inactive regions of the silicon die, referred to as dark silicon. This paper presents a reconfigurable architecture to enable effective fine-grained power gating of unused Logic Blocks (LBs) in FPGAs. In the proposed architecture, the traditional soft logic is replaced with Mega Cells (MCs), each consists of a set of complementary Generic Reconfigurable Hard Logic (GRHL) and a conventional... 

    Closing leaks: Routing against crosstalk side-channel attacks

    , Article 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2020, 23 February 2020 through 25 February 2020 ; 2020 , Pages 197-203 Seifoori, Z ; Mirzargar, S. S ; Stojilović, M ; Sharif University of Technology
    Association for Computing Machinery, Inc  2020
    Abstract
    This paper presents an extension to PathFinder FPGA routing algorithm, which enables it to deliver FPGA designs free from risks of crosstalk attacks. Crosstalk side-channel attacks are a real threat in large designs assembled from various IPs, where some IPs are provided by trusted and some by untrusted sources. It suffices that a ring-oscillator based sensor is conveniently routed next to a signal that carries secret information (for instance, a cryptographic key), for this information to possibly get leaked. To address this security concern, we apply several different strategies and evaluate them on benchmark circuits from Verilog-to-Routing tool suite. Our experiments show that, for a... 

    Polynomial datapath optimization using partitioning and compensation heuristics

    , Article Proceedings - Design Automation Conference, 26 July 2009 through 31 July 2009, San Francisco, CA ; 2009 , Pages 931-936 ; 0738100X (ISSN); 9781605584973 (ISBN) Sarbishei, O ; Alizadeh, B ; Fujita, M ; Sharif University of Technology
    2009
    Abstract
    Datapath designs that perform polynomial computations over Z 2n are used in many applications such as computer graphics and digital signal processing domains. As the market of such applications continues to grow, improvements in high-level synthesis and optimization techniques for multivariate polynomials have become really challenging. This paper presents an efficient algorithm for optimizing the implementation of a multivariate polynomial over Z2n in terms of the number of multipliers and adders. This approach makes use of promising heuristics to extract more complex common sub-expressions from the polynomial compared to the conventional methods. The proposed algorithm also utilizes a...