Sharif Digital Repository

Recent advances in VLSI technologies have enabled current silicon dies to accommodate billions of transistors in the design of very complex System-on-Chips (SoCs). To address the resulting complexity, Network-on-Chips (NoCs) have emerged as a paradigm to design scalable communication architecture to connect the processing cores of an SoC. However, smaller feature sizes, lower voltage levels and higher frequencies in Deep Sub-Micron (DSM) technologies make NoCs highly susceptible to transient faults, e.g., crosstalks, particle strikes, electro-magnetic interferences, and power supply disturbances. Single Event Upsets (SEUs) caused by high energy particle strikes as well as crosstalks are the... 

Recent advances in Very-Large-Scale Integration (VLSI) technologies have enabled designers to integrate a large number of Processing Elements (PEs) on a single die. According to International Technology Roadmap for Semiconductors (ITRS), the number of PEs will reach 5000 on a single die in 2021. Although the main achievements of such rapid advancement in chips are high processing speed, shrinkage of technology size has made chips highly sensitive to different challenges. Networks on chip (NoCs), as an example of these systems, are not exempted from these challenges. Crosstalk fault is one of the major fault resources in NoCs. Crosstalk faults occur due to coupling capacitances between... 

One of the major challenges that threat the reliability of NoC-based systems is Crosstalk fault. Some effects of crosstalk fault such as Rising/falling delays and rising/falling speed-ups lead to the variations in channel delay, incorrect data transmission, and extra power consumption in NoC communication channels. Crosstalk fault is data dependent and the intensity of this fault seriously depends on the transition patterns appearing on the wire during the data traversal between processing elements. Most of mechanisms tackling crosstalk fault that are discussed in literature are based on 3-wire delay model. In 3-wire delay model, one wire is considered as victim wire and classification of... 

Use of nano-scale VLSI technologies in the fabrication of System-on-Chips (SoCs) makes reliability as one of the major issues in the design and implementation of these products. SoCs are susceptible to several fault sources such as crosstalks, cosmic particle strikes, electromagnetic interferences, and power supply disturbances. Among the mentioned fault sources, crosstalks have the major contribution in threatening the reliability of SoCs. This thesis addresses the modeling and mitigation of crosstalk faults. In this regard, two analytical models and three crosstalk reduction methods have been introduced. The proposed analytical models, which have been introduced in the fourth chapter of... 

Technology node scaling in recent decades ushered in gate delay cut-off and rise of interconnection latency. Hence, interconnects have become a major performance bottleneck of high performance system-on-chips (SoC) and integrated circuits (IC). In addition, interconnectiosns have become more susceptible to noises in particular crosstalk. On the other hand, the advent of multi-core processors with ever increasing number of cores has highlighted the need for fast and reliable interconnections. One of the potential solutions to alleviate the interconnection delay problem is the three dimensional integration using through-silicon vias (TSV). Vertical integration of IC dies using TSVs offers high...