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Design and Implementation of Ku-Band Variable Gain Amplifier in 0.18μm CMOS Technology
, M.Sc. Thesis Sharif University of Technology ; Medi, Ali (Supervisor)
Abstract
In this thesis, a Ku-band (16.3-17.3) Variable Gain Amplifier (VGA) for realizing a phase array T/R module is designed, implemented and measured in CMOS 0.18μm technology. In order to achieve a maximum gain of 15dB and NF of 4.3dB and with the idea of improving the 1-dB compression point, two gain-stages and a novel inter-stage is proposed according to pre-distortion method. Applying this linearizing technique, makes it possible to get output P-1dB higher than 18dBm. Current steering technique is used for gain control mechanism. Gain tunabality range of 31.5dB is needed and this forces 6-bit operation with 0.5dB gain-step for the VGA. Because of loading effect of higher bits on the lower...
Design and Implementation of X-Ku Band Variable Gain Amplifier in CMOS Technology
, M.Sc. Thesis Sharif University of Technology ; Medi, Ali (Supervisor)
Abstract
In this thesis, a new wide band variable gain distributed amplifier (VGDA) is presented. A novel approach to implement uniform gain control in the wide band frequency range of 8 – 18 GHz is demonstrated. A different technique has been employed to provide necessary DC bias current, avoiding large DC-Feed inductors. A five-section wideband VGDA has been designed and fabricated in 0.18 μm CMOS technology. The VGDA have a flat gain of 11 dB, noise figure better than 5 dB, P1dB of 14 dBm at the output, input and output matching better than -12 dB and -14 dB, respectively, for maximum gain state over the 10 GHz UWB band. The gain control range is between 3 – 11 dB with gain steps of 0.5 dB and rms...
A low voltage 14-bit self-calibrated CMOS DAC with enhanced dynamic linearity
, Article Analog Integrated Circuits and Signal Processing ; Volume 43, Issue 2 , 2005 , Pages 137-145 ; 09251030 (ISSN) ; Mehrmanesh, S ; Atarodi, M ; Sharif University of Technology
2005
Abstract
A 1-V CMOS current steering digital to analog converter with enhanced static and dynamic linearity is presented. The 14-bit static linearity is achieved by a background analog self calibration technique which is suitable for low voltage applications and does not require error measurement and correction circuits. To improve dynamic linearity at high frequencies a track/attenuate output stage is used at the DAC output. Integral and differential nonlinearities of the proposed DAC corresponding to 14-bit specification are less than 0.35 and 0.25 LSB respectively. The DAC is functional up to 400MS/s with SFDR better than 71 dB in the Nyquist band. The circuit has been designed and simulated in a...
A highly-linear dual-gain CMOS low-noise amplifier for X-band
, Article IEEE Transactions on Circuits and Systems II: Express Briefs ; 2017 ; 15497747 (ISSN) ; Piri, M ; Medi, A ; Sharif University of Technology
Abstract
A highly linear X-band low-noise amplifier (LNA) is proposed and implemented in a standard 0.18-μm CMOS technology. The LNA features both high and low-gain operation modes. In its normal high-gain mode, the LNA shows a small-signal gain of 13.6 dB with an IIP3 of +9.5 dBm and a noise figure of 4.7 dB. The two-stage amplifier draws 90 mA from the 3.3V power supply to achieve +14.8 dBm output P1dB (+2.2 dBm input P1dB). In the low-gain mode, the gain is reduced by about 10 dB to further enhance the linearity and to accommodate very large blockers. Accordingly, the input P1dB is enhanced to +13.7 dBm while the noise figure is increased by 8.1 dB. A technique is also introduced to maintain the...
5-6 GHz dual-vector phase shifter in 0.18 μm LID CMOS
, Article 27th Iranian Conference on Electrical Engineering, ICEE 2019, 30 April 2019 through 2 May 2019 ; 2019 , Pages 82-86 ; 9781728115085 (ISBN) ; Fakharzadeh, M ; Safarian, A ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2019
Abstract
In this paper, a low power active phase shifter in 0.18 μm CMOS technology, operating from 5 to 6 GHz, for WLAN applications is presented. Design equations for this novel structure, which consists of two current steering stages, transconductance stage and DACs, are derived, thoroughly. This phase shifter has a range of 360° with 5.625° phase resolution. The power consumption is 35 mW. The RMS phase error is only 0.3°. The simulated power gain, input P1dB, and NF are 4 dB, -0.8 dBm and 6 dB, respectively