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data-storage-equipment
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Self-assembled one-pot synthesis of red luminescent CdS:Mn/Mn(OH)2 nanoparticles
, Article Journal of Luminescence ; Volume 128, Issue 12 , December , 2008 , Pages 1980-1984 ; 00222313 (ISSN) ; Taghavinia, N ; Iraji Zad, A ; Mahdavi, S. M ; Sharif University of Technology
2008
Abstract
We report a novel method of growing red luminescent (635 nm) Mn-doped CdS (CdS:Mn) nanoparticles capped by an inorganic shell of Mn(OH)2. CdSO4, Na2S2O3 and Mn(NO3)2 were used as the precursors, and thioglycerol (C3H8O2S) was employed as the capping agent and also the catalyst of the reaction. Using these materials resulted in very slow rate of the reaction and particles growth. The self-assembled one-pot process was performed at pH of 8 and Mn:Cd ratio of 10, and took about 10 days for completion. CdS:Mn nanoparticles are slowly formed in the first day of the process; however, the luminescence is weak. After 7 days, the solution turns white turbid through the formation of additional...
Network-on-SSD: A scalable and high-performance communication design paradigm for SSDs
, Article IEEE Computer Architecture Letters ; Vol. 12, issue 1, Article number 6178186 , 2013 , pp. 5-8 ; ISSN: 15566056 ; Arjomand, M ; Sarbazi-Azad, H ; Sharif University of Technology
Abstract
In recent years, flash memory solid state disks (SSDs) have shown a great potential to change storage infrastructure because of its advantages of high speed and high throughput random access. This promising storage, however, greatly suffers from performance loss because of frequent ''erase-before-write'' and ''garbage collection'' operations. Thus, novel circuit-level, architectural, and algorithmic techniques are currently explored to address these limitations. In parallel with others, current study investigates replacing shared buses in multi-channel architecture of SSDs with an interconnection network to achieve scalable, high throughput, and reliable SSD storage systems. Roughly...
Network-on-SSD: A scalable and high-performance communication design paradigm for SSDs
, Article IEEE Computer Architecture Letters ; Volume 12, Issue 1 , January-June , 2013 , Pages 5-8 ; 15566056 (ISSN) ; Arjomand, M ; Sarbazi Azad, H ; Sharif University of Technology
2013
Abstract
In recent years, flash memory olid state disks (SSDs) have shown a great potential to change storage infrastructure because of its advantages of high speed and high throughput random access. This promising storage, however, greatly suffers from performance loss because of frequent ''erase-before-write'' and ''garbage collection'' operations. Thus, novel circuit-level, architectural, and algorithmic techniques are currently explored to address these limitations. In parallel with others, current study investigates replacing shared buses in multi-channel architecture of SSDs with an interconnection network to achieve scalable, high throughput, and reliable SSD storage systems. Roughly speaking,...
Towards an architecture for real-time data storage
, Article Proceedings - 2nd International Conference on Computational Intelligence, Modelling and Simulation, CIMSim 2010, 28 September 2010 through 30 September 2010 ; 2010 , Pages 279-284 ; 9780769542621 (ISBN) ; Habibi, J ; Ahmadi, H ; Vatanian Shanjani, G ; Sharif University of Technology
Abstract
Nowadays, due to the growing role that analytical, predictive and decision making activities perform in organizations, organizational data are very important. In order to utilizing organizational data, it should be transmitted from the operational and transactional environment to a dimensional or normal database. However, not only differences in platforms and data types are some issues that should be overcome, but also variety of data types such as non-structural and text format files should be considered. In this way, exploiting updated data storages is necessary for quick and accurate services and raising customers' satisfaction. Although real time data storages are frequently used in...
Endurance-aware security enhancement in non-volatile memories using compression and selective encryption
, Article IEEE Transactions on Computers ; Volume 66, Issue 7 , 2017 , Pages 1132-1144 ; 00189340 (ISSN) ; Sarbazi Azad, H ; Sharif University of Technology
Abstract
Emerging non-volatile memories (NVMs) are notable candidates for replacing traditional DRAMs. Although NVMs are scalable, dissipate lower power, and do not require refreshes, they face new challenges including shorter lifetime and security issues. Efforts toward securing the NVMs against probe attacks pose a serious downside in terms of lifetime. Cryptography algorithms increase the information density of data blocks and consequently handicap the existing lifetime enhancement solutions like Flip-N-Write. In this paper, based on the insight that compression can relax the constraints of lifetime-security trade-off, we propose CryptoComp, an architecture that, taking the advantage of block size...
A low energy soft error-tolerant register file architecture for embedded processors
, Article 11th IEEE High Assurance Systems Engineering Symposium, HASE 2008, Nanjing, 3 December 2008 through 5 December 2008 ; December , 2008 , Pages 109-116 ; 15302059 (ISSN); 9780769534824 (ISBN) ; Ahmadian, S. N ; Miremadi, S. G ; Nanjing University; IEEE Computer Society; IEEE Reliability Society ; Sharif University of Technology
2008
Abstract
This paper presents a soft error-tolerant architecture to protect embedded processors register files. The proposed architecture is based on selectively duplication of the most vulnerable registers values in a cache memory embedded beside the processor register file so called register cache. To do this, two parity bits are added to each register of the processor to detect up to three contiguous errors. To recover the erroneous register value, two distinct cache memories are utilized for storing the redundant copy of the vulnerable registers, one for short lived registers and the other one for long lived registers. The proposed method has two key advantageous as compared to fully ECC protected...
Development of a hybrid dynamic programming approach for solving discrete nonlinear knapsack problems
, Article Applied Mathematics and Computation ; Volume 188, Issue 1 , 2007 , Pages 1023-1030 ; 00963003 (ISSN) ; Jahangiri, E ; Sharif University of Technology
2007
Abstract
A multiple-choice knapsack problem can be formulated as a discrete nonlinear knapsack problem (DNKP). A powerful method for solving DNKP is the dynamic programming solution approach. The use of this powerful approach however is limited since the growth of the number of decision variables and state variables requires an extensive computer memory storage and computational time. In this paper we developed a hybrid algorithm for improving the computational efficiency of the dynamic programming when it is applied for solving the DNKP. In the hybrid algorithm, three routines of the imbedded state, surrogate constraints, and bounding scheme are incorporated for increasing the efficiency of this...
Two-phase prediction of L1 data cache misses
, Article IEE Proceedings: Computers and Digital Techniques ; Volume 153, Issue 6 , 2006 , Pages 381-388 ; 13502387 (ISSN) ; Jahangir, A. H ; Sharif University of Technology
2006
Abstract
Hardware prefetching schemes which divide the misses into streams are generally preferred to other hardware based schemes. But, as they do not know when the next miss of a stream happens, they cannot prefetch a block in appropriate time. Some of them use a substantial amount of hardware storage to keep the predicted miss blocks from all streams. The other approaches follow the program flow and prefetch all target addresses including those blocks which already exist in the L1 data cache. The approach presented predicts the stream of next miss and then prefetches only the next miss address of the stream. It offers a general prefetching framework, two-phase prediction algorithm (TPP), that lets...
On the performance of trace locality of reference
, Article Performance Evaluation ; Volume 60, Issue 1-4 , 2005 , Pages 51-72 ; 01665316 (ISSN) ; Jahangir, A. H ; Gholamipour, A. H ; Sharif University of Technology
Elsevier
2005
Abstract
In this paper, trace locality of reference (LoR) is identified as a mechanism to predict the behavior of a variety of systems. If two objects were accessed nearby in the past and the first one is accessed again, trace LoR predicts that the second one will be accessed in near future. To capture trace LoR, trace graph is introduced. Although trace LoR can be observed in a variety of systems, but the focus of this paper is to characterize it for data accesses in memory management systems. In this field, it is compared with recency-based prediction (LRU stack) and it is shown that not only the model is much simpler, but also it outperforms recency-based prediction in all cases. The paper...
SkipTree: A Scalable range-queryable distributed data structure for multidimensional data
, Article 16th International Symposium on Algorithms and Computation, ISAAC 2005, Hainan, 19 December 2005 through 21 December 2005 ; Volume 3827 LNCS , 2005 , Pages 298-307 ; 03029743 (ISSN); 3540309357 (ISBN); 9783540309352 (ISBN) ; Toossi, M ; Ghodsi, M ; Sharif University of Technology
2005
Abstract
This paper presents the SkipTree, a new balanced, distributed data structure for storing data with multidimensional keys in a peer-to-peer network. The SkipTree supports range queries as well as single point queries which are routed in O(log n) hops. SkipTree is fully decentralized with each node being connected to O(logn) other nodes. The memory usage for maintaining the links at each node is O(log n log log n) on average and O(log2 n) in the worst case. Load balance is also guaranteed to be within a constant factor. © Springer-Verlag Berlin Heidelberg 2005
Emerging non-volatile memory technologies for future low power reconfigurable systems
, Article 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, ReCoSoC ; 26-28 May , 2014 , pp. 1-2 ; 9781479958108 ; Asadi, H ; Tahoori, M. B ; Sharif University of Technology
Abstract
Non-volatile memory (NVM) technologies are promising alternatives to traditional CMOS memory technologies. While NVMs were primarily studied to be used in the memory hierarchy, they can also provide benefits in reconfigurable systems such as Field-Programmable Gate Arrays (FPGAs). In this paper, we investigate the applicability of different NVM technologies for the configuration bits of FPGAs and propose a power-efficient reconfigurable architecture based on Phase Change Memory (PCM). Quantitative analysis for various FPGA architectures using different memory technologies shows the benefits of the proposed scheme
FTSPM: A fault-tolerant scratchpad memory
, Article Proceedings of the International Conference on Dependable Systems and Networks ; 2013 , Page(s): 1 - 10 ; 9781467364713 (ISBN) ; Farbeh, H ; Miremadi, S. G ; Fazeli, M ; Asadi, H ; Sharif University of Technology
2013
Abstract
Scratch Pad Memory (SPM) is an important part of most modern embedded processors. The use of embedded processors in safety-critical applications implies including fault tolerance in the design of SPM. This paper proposes a method, called FTSPM, which integrates a multi-priority mapping algorithm with a hybrid SPM structure. The proposed structure divides SPM into three parts: 1) a part is equipped with Non-Volatile Memory (NVM) which is immune against soft errors, 2) a part is equipped with Error-Correcting Code, and 3) a part is equipped with parity. The proposed mapping algorithm is responsible to distribute the program blocks among the above three parts with regards to their vulnerability...
A network coding-based packet forwarding scheme for unicast random access networks with exponential backoff
, Article 2013 Iran Workshop on Communication and Information Theory ; May , 2013 , Page(s): 1 - 6 ; 9781467350235 (ISBN) ; Ashtiani, F ; Sharif University of Technology
2013
Abstract
Exponential backoff is an intrinsic feature of MAC-layer standards of most types of ad hoc networks. It leads to random access channels with memory. In this paper we propose a new network coding-based packet forwarding scheme suitable for multiple unicast scenarios in downlink direction of a wireless network. The wireless nodes as well as the access point attempt to access the channel, based on slotted Aloha with exponential backoff. In the proposed scheme we convert multiple unicast scenario to a combination of several anycast and a multicast scenarios. By proposing an open multiclass queueing network, we are able to derive the maximum stable download throughput of the network. The...
Multi-objective optimization for design and operation of distributed energy systems through the multi-energy hub network approach
, Article Industrial and Engineering Chemistry Research ; Volume 55, Issue 33 , 2016 , Pages 8950-8966 ; 08885885 (ISSN) ; Sattari, S ; Roshandel, R ; Fowler, M ; Elkamel, A ; Sharif University of Technology
American Chemical Society
2016
Abstract
A generic framework is developed to study the application of energy hubs and its related network model to demonstrate the optimal design and operation of distributed energy systems (DESs) in urban areas. A novel multi-objective approach based on augmented epsilon constraint technique is employed to carry out this work. As an illustrative example, the proposed model is applied to an urban area in Ontario, Canada. Different scenarios are defined to investigate the effect of energy storage systems and energy exchange within a network on the optimal configuration and operation of the system. Moreover, multi-objective optimization is carried out based on two conflicting objectives, namely, total...
Captopril: Reducing the pressure of bit flips on hot locations in non-volatile main memories
, Article Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016, 14 March 2016 through 18 March 2016 ; 2016 , Pages 1116-1119 ; 9783981537062 (ISBN) ; Sarbazi Azad, H ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2016
Abstract
High static power consumption and insufficient scalability of the commonly used DRAM main memory technology appear to be tough challenges in upcoming years. Hence, adopting new technologies, i.e. non-volatile memories (NVMs), is a proper choice. NVMs tolerate a low number of write operations while having good scalability and low static power consumption. Due to the non-destructive nature of a read operation and the long latency of a write operation in NVMs, designers use read-before-write (RBW) mechanism to mask the unchanged bits during write operation in order to reduce bit flips. Based on this observation that some specific locations of blocks are responsible for the majority of bit...
Change detection in remote sensing images using modified polynomial regression and spatial multivariate alteration detection
, Article Journal of Applied Remote Sensing ; Volume 3, Issue 1 , 2009 ; 19313195 (ISSN) ; Kasaei, S ; Sharif University of Technology
Abstract
A new and efficient method for incorporating the spatiality into difference-based change detection (CD) algorithms is introduced in this paper. It uses the spatial derivatives of image pixels to extract spatial relations among them. Based on this methodology, the performances of two famous difference-based CD methods, conventional polynomial regression (CPR) and multivariate alteration detection (MAD), are improved and called modified polynomial regression (MPR) and spatial multivariate alteration detection (SMAD), respectively. Various quantitative and qualitative evaluations have shown the superiority of MPR over CPR and SMAD over MAD. Also, the superiority of SMAD over all mentioned CD...
Evaluating impact of human errors on the availability of data storage systems
, Article 20th Design, Automation and Test in Europe, DATE 2017, 27 March 2017 through 31 March 2017 ; 2017 , Pages 314-317 ; 9783981537093 (ISBN) ; Eftekhari, R ; Asadi, H ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2017
Abstract
In this paper, we investigate the effect of incorrect disk replacement service on the availability of data storage systems. To this end, we first conduct Monte Carlo simulations to evaluate the availability of disk subsystem by considering disk failures and incorrect disk replacement service. We also propose a Markov model that corroborates the Monte Carlo simulation results. We further extend the proposed model to consider the effect of automatic disk fail-over policy. The results obtained by the proposed model show that overlooking the impact of incorrect disk replacement can result up to three orders of magnitude unavailability underestimation. Moreover, this study suggests that by...
WIPE: wearout informed pattern elimination to improve the endurance of NVM-based caches
, Article Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 16 January 2017 through 19 January 2017 ; 2017 , Pages 188-193 ; 9781509015580 (ISBN) ; Hosseini Monazzah, A. M ; Farbeh, H ; Miremadi, S. G ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2017
Abstract
With the recent development in Non-Volatile Memory (NVM) technologies, several studies have suggested using them as an alternative to SRAMs in on-chip caches. However, limited endurance of NVMs is a major challenge when employed in the caches. This paper proposes a data manipulation technique, so-called Wearout Informed Pattern Elimination (WIPE), to improve the endurance of NVM-based caches by reducing the activity of frequent data patterns. Simulation results show that WIPE improves the endurance by up to 93% with negligible overheads. © 2017 IEEE
An analytical model for performance and lifetime estimation of hybrid DRAM-NVM main memories
, Article IEEE Transactions on Computers ; Volume 68, Issue 8 , 2019 , Pages 1114-1130 ; 00189340 (ISSN) ; Mutlu, O ; Asadi, H ; Sharif University of Technology
IEEE Computer Society
2019
Abstract
Emerging Non-Volatile Memories (NVMs) have promising advantages (e.g., lower idle power, higher density, and non-volatility) over the existing predominant main memory technology, DRAM. Yet, NVMs also have disadvantages (e.g., longer latencies, higher active power, and limited endurance). System architects are therefore examining hybrid DRAM-NVM main memories to enable the advantages of NVMs while avoiding the disadvantages as much as possible. Unfortunately, the hybrid memory design space is very large and complex due to the existence of very different types of NVMs and their rapidly-changing characteristics. Therefore, optimization of performance and lifetime of hybrid memory based...
Network-constrained optimal scheduling of multi-carrier residential energy systems: a chance-constrained approach
, Article IEEE Access ; Volume 9 , 2021 , Pages 86369-86381 ; 21693536 (ISSN) ; Ranjbar, H ; Shafie Khah, M ; Ehsan, M ; Catalão, J. P. S ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2021
Abstract
This paper presents a day-ahead scheduling approach for a multi-carrier residential energy system (MRES) including distributed energy resources (DERs). The main objective of the proposed scheduling approach is the minimization of the total costs of an MRES consisting of both electricity and gas energy carriers. The proposed model considers both electrical and natural gas distribution networks, DER technologies including renewable energy resources, energy storage systems (ESSs), and combined heat and power. The uncertainties pertinent to the demand and generated power of renewable resources are modeled using the chance-constrained approach. The proposed model is applied on the IEEE 33-bus...