Sharif Digital Repository

This paper presents a new low-power comparator-reduced hybrid ADC. The proposed ADC uses dynamic comparators to perform a high-speed low-power conversion. In order to reduce the offset and kickback noise effect of conventional dynamic comparators, a new low-kickback noise comparator with a high pre-amplifier gain is presented. Two 4bit and 8bit ADCs are designed and simulated in 0.18 μm CMOS technology with 1.8 v supply voltage. INL and DNL of 4bit ADC are less than 0.4LSB and 0.5LSB, respectively, while 8bit ADC obtains DNL and INL of 0.83LSB and 1.3LSB, respectively. With ENOB of 3.6bit and 7.2bit for 4bit and 8bit ADCs, the 4bit ADC consumes only 1.7 mW at the sampling rate of 400 Ms/s... 

This paper presents a new low-power reduced comparator flash ADC. The proposed ADC uses dynamic comparators to perform a high-speed low-power conversion. In order to reduce offset and kick-back noise effect of conventional dynamic comparators, a new comparator with a higher pre-amplifier gain along with the mathematical analysis is presented. The proposed 4bit ADC is simulated in 0.18um with 1.8-υ supply voltage. SNDR and SFDR of the ADC are 23dB and 26.5dB, respectively. The ADC consumes only 0.95mw at the sampling rate of 400MS/s. © 2017 IEEE  

This study deals with proposing a Lyapunov-based technique for stability analysis of fractional order time-delay systems. The proposed technique is constructed on the basis of modifying the convex part of a class of Lyapunov-Krasovskii functionals commonly used in stability analysis of integer order time-delay systems. As a consequence for this achievement, it is revealed that the Lyapunov-Krasovskii-based stability conditions in integer order time-delay systems can result in stability of their fractional order counterparts defined based on Caputo/Riemann-Liouville derivative operators with orders in the range (0,1). The applicability of the study results is shown through three different...