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On the importance of the number of fanouts to prevent the glitches in DPA-resistant devices
, Article 13th International Computer Society of Iran Computer Conference on Advances in Computer Science and Engineering, CSICC 2008, Kish Island, 9 March 2008 through 11 March 2008 ; Volume 6 CCIS , 2008 , Pages 661-670 ; 18650929 (ISSN); 3540899847 (ISBN); 9783540899846 (ISBN) ; Salmasizadeh, M ; Manzuri Shalmani, M. T ; Sharif University of Technology
2008
Abstract
During the last years several logic styles have been proposed to counteract power analysis attacks. This article starts with a brief review of four different logic styles namely RSL, MDLP, DRSL, and TDPL. This discussion continues to examine the effect of the number of fanouts in power consumption of a CMOS inverter. Moreover, it is shown that insertion of delay elements in typical CMOS circuits is not adequate to prevent the glitches and information leakage unless the fanouts of input signals are balanced. Whereas enable signals have to be classified according to the depth of combinational circuits implemented using pre-charge logic styles, we show that the number of fanouts of enable...
Time to Digital Converters for ADPLL Applications
, Ph.D. Dissertation Sharif University of Technology ; Hajsadeghi, Khosrow (Supervisor)
Abstract
Effect of resolution of Time to Digital Converters (TDCs) on the performance of All-Digital Phase Locked Loops (ADPLLs) and capability of achieving higher resolution in advanced technologies lead to introducing different kinds of TDCs. Beside the analysis of different kinds of TDCs, This thesis proposes three new TDCs based on the time amplifi-cation concept. A new pipeline TDC is designed using a wide dynamic range time amplifi-er. A new method is used to widen dynamic range of the conventional time amplifiers. In order to get a low power high resolution conversion, a new delay element design is devel-oped to reduce the delay value and its sensitivity to mismatch and process variations....
A power efficient masking technique for design of robust embedded systems against SEUs and SETs
, Article 23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2008, Boston, MA, 1 October 2008 through 3 October 2008 ; October , 2008 , Pages 193-201 ; 15505774 (ISSN) ; Miremadi, S. G ; Sharif University of Technology
2008
Abstract
In this paper, an SET and SEU tolerant latch suitable for use in embedded systems called SETUR (Single Event Transient and Upset Robust latch) is presented and evaluated. The SETUR is based on the use of a redundant feedback line and a CMOS delay element to tolerate the effect of the SETs occurring in the input line of the latch as well as SEUs occurring inside the latch. The experimental results show that the probability of an SET resulting in a soft error can be reduced up to 90% by choosing a proper delay value. The soft error rate of the SETUR due to SEUs occurring inside the latch is reduced by 95% while having lower area, power and performance overhead than the previously proposed...
Latency considerations in IEC 61850-enabled substation automation systems
, Article IEEE Power and Energy Society General Meeting, 24 July 2011 through 28 July 2011, Detroit, MI ; 2011 ; 19449925 (ISSN) ; 9781457710018 (ISBN) ; Mousavi, M. J ; Vakilian, M ; Sharif University of Technology
Abstract
Substation Automation Systems (SAS) offer powerful, fast, and viable ways to design, automate, and implement substation protection, control, and monitoring functions in modern transmission and distribution grids. Today's SAS -more than ever- rely on the adoption of IEC61850 as a worldwide standard for interoperability and dependable peer-to-peer and substation communications. Being based on the Ethernet computer networking technology, the reliability issues associated with latency in 61850-enabled SAS is of a design consideration. Unpredictability is the most important challenge for latency assessment. This paper discusses the background framework for latency evaluations in SAS by...
Low energy single event upset/single event transient-tolerant latch for deep subMicron technologies
, Article IET Computers and Digital Techniques ; Volume 3, Issue 3 , 2009 , Pages 289-303 ; 17518601 (ISSN) ; Miremadi, S. G ; Ejlali, A ; Patooghy, A ; Sharif University of Technology
2009
Abstract
Single event upsets (SEUs) and single event transients (SETs) are major reliability concerns in deep submicron technologies. As technology feature size shrinks, digital circuits are becoming more susceptible to SEUs and SETs. A novel SEU/SET-tolerant latch called feedback redundant SEU/SET-tolerant latch (FERST) is presented, where redundant feedback lines are used to mask SEUs and delay elements are used to filter SETs. Detailed SPICE simulations have been done to evaluate the proposed design and compare it with previous latch designs. The results show that the SEU tolerance of the FERST latch is almost equal to that of a TMR latch (a widely used latch which is the most reliable among the...