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    Error detection enhancement in COTS superscalar processors with performance monitoring features

    , Article Journal of Electronic Testing: Theory and Applications (JETTA) ; Volume 20, Issue 5 SPEC.ISS , 2004 , Pages 553-567 ; 09238174 (ISSN) Rajabzadeh, A ; Miremadi, S. G ; Mohandespour, M ; Sharif University of Technology
    Increasing use of commercial off-the-shelf (COTS) superscalar processors in industrial, embedded, and real-time systems necessitates the development of error detection mechanisms for such systems. This paper presents an error detection scheme called Committed Instructions Counting (CIC) to increase error detection in such systems. The scheme uses internal Performance Monitoring features and an external watchdog processor (WDP). The Performance Monitoring features enable counting the number of committed instructions in a program. The scheme is experimentally evaluated on a 32-bit Pentium® processor using software implemented fault injection (SWIFI). A total of 8181 errors were injected into... 

    Control-flow checking using branch instructions

    , Article 5th International Conference on Embedded and Ubiquitous Computing, EUC 2008, Shanghai, 17 December 2008 through 20 December 2008 ; Volume 1 , January , 2008 , Pages 66-72 ; 9780769534923 (ISBN) Jafari Nodoushan, M ; Miremadi, S. G ; Ejlali, A ; IEEE Computer Society Technical Committee on Scalable Computing ; Sharif University of Technology
    This paper presents a hardware control-flow checking scheme for RISC processor-based systems. This Scheme combines two error detection mechanisms to provide high coverage. The first mechanism uses parity bits to detect faults occurring in the opcodes and in the target addresses of branch instructions which lead to erroneous branches. The second mechanism uses signature monitoring to detect errors occurring in the sequential instructions. The scheme is implemented using a watchdog processor for an VHDL model of the LEON2 processor. About 31800 simulation faults were injected into the LEON2 processor. The results show that the error detection coverage is about 99.5% with average detection... 

    Energy Efficient Concurrent Test of Switches and Links for Networks-On-Chip

    , M.Sc. Thesis Sharif University of Technology Alamian, Sanaz (Author) ; Hessabi, Shahin (Supervisor)
    Nowadays by increasing the number of processing cores in system-on-chip, using networks-on-chip, as an optimized interconnection foundation for transferring data between processing cores is inevitable .Based on this, the necessity of designing and implementing an optimized structure for testing network-on-chip, considering various overheads such as power consumption, latency, bandwidth and area, becomes an important issue in designing network-on-chip. The purpose of this project is to design an optimized structure for testing routers and connecting links in network, which considers power consumption overhead, latency and area overhead on one hand, and fault coverage on the other hand.... 

    A low cost circuit level fault detection technique to full adder design

    , Article 2011 18th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2011, 11 December 2011 through 14 December 2011, Beirut ; 2011 , Pages 446-450 ; 9781457718458 (ISBN) Mozafari, S. H ; Fazeli, M ; Hessabi, S ; Miremadi, S. G ; Sharif University of Technology
    This paper proposes a Low Cost circuit level Fault Detection technique called LCFD for a one-bit Full Adder (FA) as the basic element of adder circuits. To measure the fault detection coverage of the proposed technique, we conduct an exhaustive circuit level fault injection experiment on all susceptible nodes of a FA. Experimental results show that the LCDF technique can detect about 83% of injected faults while having only about 40% area and 22% power consumption overheads. In the LCDF technique, the fault detection latency does not affect the latency of the FA, since the error detection is done in parallel with the addition  

    RT-Level Test Pattern Generation with Horner Expansion Model

    , Ph.D. Dissertation Sharif University of Technology Mirzaei, Mohammad (Author) ; Tabandeh, Mahmoud (Supervisor) ; Navabi, Zainalabedin (Co-Advisor)
    Increasing in size and complexity of digital designs has made manufacturing process more complex and enforces more complexity in verification of designs. This makes it essential to address critical verification issues at the early stages of design cycle. Such a complicated designs needs to be tested for fabrication faults as well as functional faults. Several attempts have been made to raise the quality of testing methods with automatic test pattern generation (ATPG) and design for testability (DFT) methods in logic and lower levels. Although these techniques try to increase the testability of a circuit considerably, but there are always some overheads in area, power and performance.... 

    Feature specific control flow checking in COTS-based embedded systems

    , Article Proceedings - 3rd International Conference on Dependability, DEPEND 2010, 18 July 2010 through 25 July 2010 ; July , 2010 , Pages 58-63 ; 9780769540900 (ISBN) Rajabzadeh, A ; Miremadi, S.G ; IARIA ; Sharif University of Technology
    While the Control Flow Checking (CFC) methods are using the ordinary instruction set and general Arithmetic and Logic Unit (ALU) features to protect the programs against the transient faults, this paper presents a new kind of CFC method, called feature specific CFC. The idea behind this method is using a specific internal hardware in modern processors which provides the ability to monitor internal various parameters of the program. This method is a pure software method and the external hardware overhead is zero. Other overheads have been measured experimentally by executing the workloads on a Pentium system. The execution time overhead is between 42% and 67% and the program size overhead is... 

    Experimental evaluation of three concurrent error detection mechanisms

    , Article 2006 International Conference on Microelectronics, ICM 2006, Dhahran, 16 December 2006 through 19 December 2006 ; 2006 , Pages 67-70 ; 1424407656 (ISBN); 9781424407651 (ISBN) Vahdatpour, A ; Fazeli, M ; Miremadi, S. G ; Sharif University of Technology
    This paper presents an experimental evaluation of the effectiveness of three hardware-based control flow checking mechanisms, using software-implemented fault injection (SWIFI) method. The fault detection technique uses reconfigurable of the shelf FPGAs to concurrently check the execution flow of the target program. The technique assigns signatures to the target program in the compile time and verifies the signatures using a FPGA as a watchdog processor to detect possible violation caused by the transient faults. A total of 3000 faults were injected in the experimental embedded system, which is based on an 8051 microcontroller, to measure the error detection coverage. The experimental...