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    Control-flow checking using branch instructions

    , Article 5th International Conference on Embedded and Ubiquitous Computing, EUC 2008, Shanghai, 17 December 2008 through 20 December 2008 ; Volume 1 , January , 2008 , Pages 66-72 ; 9780769534923 (ISBN) Jafari Nodoushan, M ; Miremadi, S. G ; Ejlali, A ; IEEE Computer Society Technical Committee on Scalable Computing ; Sharif University of Technology
    This paper presents a hardware control-flow checking scheme for RISC processor-based systems. This Scheme combines two error detection mechanisms to provide high coverage. The first mechanism uses parity bits to detect faults occurring in the opcodes and in the target addresses of branch instructions which lead to erroneous branches. The second mechanism uses signature monitoring to detect errors occurring in the sequential instructions. The scheme is implemented using a watchdog processor for an VHDL model of the LEON2 processor. About 31800 simulation faults were injected into the LEON2 processor. The results show that the error detection coverage is about 99.5% with average detection... 

    A low cost circuit level fault detection technique to full adder design

    , Article 2011 18th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2011, 11 December 2011 through 14 December 2011, Beirut ; 2011 , Pages 446-450 ; 9781457718458 (ISBN) Mozafari, S. H ; Fazeli, M ; Hessabi, S ; Miremadi, S. G ; Sharif University of Technology
    This paper proposes a Low Cost circuit level Fault Detection technique called LCFD for a one-bit Full Adder (FA) as the basic element of adder circuits. To measure the fault detection coverage of the proposed technique, we conduct an exhaustive circuit level fault injection experiment on all susceptible nodes of a FA. Experimental results show that the LCDF technique can detect about 83% of injected faults while having only about 40% area and 22% power consumption overheads. In the LCDF technique, the fault detection latency does not affect the latency of the FA, since the error detection is done in parallel with the addition