Sharif Digital Repository

Multicomputers have experienced a rapid development during the last decade. Multicomputers rely on an interconnection network among processors to support the message-passing mechanism. Therefore, the reliability of the interconnection network is very important for the reliability of the whole system. In this paper a new fault-tolerant routing algorithm, which is based on dimension order routing, is proposed for k-ary 2-cubes. Packets are sent to their destination through XY routing algorithm and if this transmission is not possible, YX routing algorithm is applied. The XY routing algorithm nullifies offset in "X" direction before routing in "Y" direction, but the YX routing algorithm first... 

With the advent in technology and shrinking the transistor size down to nano scale, static power may become the dominant power component in Networks-on-Chip (NoCs). Powergating is an efficient technique to reduce the static power of under-utilized resources in different types of circuits. For NoC, routers are promising candidates for power gating, since they present high idle time. However, routers in a NoC are not usually idle for long consecutive cycles due to distribution of resources in NoC and its communication-based nature, even in low network utilizations. Therefore, power-gating loses its efficiency due to performance and power overhead of the packets that encounter powered-off... 

Reducing the size of the technology increases leakage power in Network-on-Chip (NoC) routers drastically. Power-gating, particularly in NoC routers, is one of the most efficient approaches for alleviating the leakage power. Although applying power-gating techniques alleviates NoC power consumption due to high proportion of idleness in NoC routers, since the timing behavior of packets is irregular, even in low injection rates, performance overhead in power-gated routers is significant. In this paper, we present SMART, a Scalable Mapping And Routing Technique, with virtually no area overhead on the network. It improves the irregularity of the timing behavior of packets in order to mitigate... 

In this paper, we propose a new architecture for nanophotonic Networks on Chip (NoC), named 2D-HERT, which consists of optical data and control planes. The proposed data plane is built upon a new topology and all-optical switches that passively route optical data streams based on their wavelengths. Utilizing wavelength routing method, the proposed deterministic routing algorithm, and Wavelength Division Multiplexing (WDM) technique, the proposed data plane eliminates the need for optical resource reservation at the intermediate nodes. For resolving end-point contention, we propose an all-optical request-grant arbitration architecture which reduces optical losses compared to the alternative... 

This paper proposes new architectures for data and control planes in a nanophotonic networks-on-chip (NoC) with the key advantages of scalability to large scale networks, constant node degree, and simplicity. Moreover, we propose a minimal deterministic routing algorithm for the data network which leads to small and simple photonic switches. Built upon the proposed novel topology, we present a scalable all-optical NoC, referred to as 2D-HERT, which offers passive routing of optical data streams based on their wavelengths. Utilizing wavelength routing method, Wavelength Division Multiplexing (WDM) technique, and a new all-optical control architecture, our proposed optical NoC eliminates the... 

This paper proposes a novel topology for optical Network on Chip (NoC) architectures with the key advantages of regularity, vertex symmetry, scalability to large scale networks, constant node degree, and simplicity. Moreover, we propose a minimal deterministic routing algorithm for the proposed topology which leads to small and simple photonic routers. Built upon our novel network topology, we present a scalable all-optical NoC, referred to as 2D-HERT, which offers passive routing of optical data streams based on their wavelengths. Utilizing wavelength routing method along with Wavelength Division Multiplexing technique, our proposed optical NoC eliminates the need for electrical resource... 

A routing algorithm defines a route which packet traverses to get to destination. In this research we study some kind of routing algorithms that are used in internal connections networks of multi-processor and multi-computers systems. Then we discuss about some routing algorithms which have been implemented network on chip architecture. First, we present a group of routing algorithms based on various criterions, and review so-called category. Afterwards, we study adaptive and deterministic routing algorithms and express circular model applying in internal connections networks and its governing rules in order to prevent dead lock. Then we survey adaptive algorithms such as Deflection routing,...