Sharif Digital Repository

Composite field arithmetic is known as an alternative method for lookup tables in implementation of S-box block of AES algorithm. The idea is to breakdown the computations to lower order fields and compute the inverse there. Recently this idea have been used both for reducing the area in implementation of S-boxes and masking implementations of AES algorithm. The most compact design using this technique is presented by Canright using only 92 gates for an S-box block. In another approach, IAIK laboratory has presented a masked implementation of AES algorithm with higher security comparing common masking methods using Composite field arithmetic. Our work in this paper is to use basic ideas of... 

This paper presents a new cache scheme based on varying the size of sets in the set-associative cache hierarchically. In this scheme, all sets at a hierarchical level have same size but are fc times more than the size of sets in the next level of hierarchy where k is called division factor. Therefore the size of tag fields associated to each set is variable and it depends on the hierarchy level of the set it is in. This scheme is proposed to achieve higher hit ratios with respect to the two conventional schemes namely set-associative and direct mapping. The proposed scheme has been simulated with several standard trace files SPEC 2000 and statistics are gathered and analyzed for different... 

In search of low cost and flexible substrates organic transistors have been suggested as an alternate to silicon transistors. Level 1 model extraction, investigating different circuit styles and proposing two new circuit styles for organic integrated circuits is done in this paper. First, level 1 model of organic transistor is found using ID-VDS characteristics of transistors reported by [9]. After that different design styles used in CMOS digital integrated circuits are reviewed and the functionality of these styles for organic integrated circuits is investigated. Two new circuit styles have been proposed in this section which have better performance for organic circuits comparing with... 

In this paper, we propose a novel approach to extract a network of half adders from the gate-level net-list of an addition circuit while no internal equivalences exist. The technique begins with a gatelevel net-list and tries to map it into word-level adders based on an efficient bit-level adder representation. It will be shown that the proposed technique is suitable for several gate-level architectures of multipliers, as it extracts adder components in a step-wise method. This approach can also be generalized to other arithmetic circuits. In order to evaluate the effectiveness of our approach, we run it on several arithmetic circuits and compare experimental results with those of... 

We study here the algorithmic analysis of systems modeled in terms of availability languages. Our first main result is a positive answer to the emptiness problem: it is decidable whether a given availability language contains a word. The key idea is an inductive construction that replaces availability languages with Parikh-equivalent regular languages. As a second contribution, we solve the intersection problem modulo bounded languages: given availability languages and a bounded language, it is decidable whether the intersection of the former contains a word from the bounded language. We show that the problem is NP-complete. The idea is to reduce to satisfiability of existential Presburger... 

Abstract BCD digit multiplication module (BDM) is widely used in BCD arithmetic, especially in Decimal Floating-Point (DFP) units. In this paper, we present a new BCD digit multiplication scheme to accelerate this module. Similar to previous articles, our multiplier includes two parts contained binary multiplier and binary to BCD converter. Our contribution towards these modules can successfully overcome the previous BCD digit multipliers. The results indicate 19% hardware acceleration for the proposed multiplier architecture which is comparable to the best previous techniques in UMC 65 nm CMOS standard cells library hardware implementation. Therefore, the proposed BCD digit multiplier is an... 

As transistor dimensions continue to shrink, long-term reliability threats, such as Negative Bias Temperature Instability, affect multicore processors lifespan. This letter proposes a load balancing technique, based on the rate of integer and floating-point instructions per workloads. This technique classifies workloads into integer-majority and floating-point-majority classes and migrates workloads among cores in order to relax the stressed execution units. The context switching feature of operating system is employed to reduce implementation and performance overheads of the proposed technique. According to the simulations, the proposed technique reduces the aging rate of a multicore... 

We introduce the notion of two-valued digit (twit) as a binary variable that can assume one of two different integer values. Posibits, or simply bits, in {0, 1} and negabits in {-1, 0}, commonly used in two's-complement representations and (n, p) encoding of binary signed digits, are special cases of twits. A weighted bit-set (WBS) encoding, which generalizes the two's-complement encoding by allowing one or more posibits and/or negabits in each radix-2 position, has been shown to unify many efficient implementations of redundant number systems. A collection of equally weighted twits, including ones with non-contiguous values (e.g., {-1, 1} or {0, 2}), can lead to wider representation range... 

DSP algorithms are one of the most important components of modern embedded computer systems. These applications generally include fixed point and floating-point arithmetic operations and trigonometric functions which have long latencies and high power consumption. Nonetheless, DSP applications enjoy from some interesting characteristics such as tolerating slight loss of accuracy and high degree of value locality which can be exploited to improve their power consumption and performance. In this paper, we present an application-specific result-cache that aims to reduce the power consumption and latency of DSP algorithms by reusing the results of the arithmetic operations executed on the same... 

DSP algorithms are one of the most important components of modern embedded computer systems. These applications generally include fixed point and floating-point arithmetic operations and trigonometric functions which have long latencies and high power consumption. Nonetheless, DSP applications enjoy from some interesting characteristics such as tolerating slight loss of accuracy and high degree of value locality which can be exploited to improve their power consumption and performance. In this paper, we present an application-specific result-cache that aims to reduce the power consumption and latency of DSP algorithms by reusing the results of the arithmetic operations executed on the same... 

In this paper, we propose two lossless compression techniques that represent a two dimensional Run-length Coding which can achieve high compression ratio. This method works by partitioning the block regions of the input image into rectangles instead of working by runs of adjacent pixels, so it is found to be more efficient than 1D RLE Run-length Coding for transmitting texts and image. In the first method, length and width of consecutive black and white rectangles are transmitted. The idea of this method is new and it can be very effective for some images which have large blocks of black or white pixels. But in the second method only black rectangles are considered in order to transmit and... 

We propose a lightweight scheme where the formation of a data block is changed in such a way that it can tolerate soft errors significantly better than the baseline. The key insight behind our work is that CNN weights are normalized between -1 and 1 after each convolutional layer, and this leaves one bit unused in half-precision floating-point representation. By taking advantage of the unused bit, we create a backup for the most significant bit to protect it against the soft errors. Also, considering the fact that in MLC STT-RAMs the cost of memory operations (read and write), and reliability of a cell are content-dependent (some patterns take larger current and longer time, while they are... 

Cartesian Genetic Programming (CGP) has an unusual genotype representation which makes it more efficient than Genetic programming (GP) in digital circuit design problem. However, to the best of our knowledge, all methods used in evolutionary design of digital circuits deal with rugged, complex search space, which results in long running time to obtain successful evolution. Therefore, employing a method to guide evolution in these spaces can facilitate achieving more reasonable results. It has been claimed that a two-step evolutionary scenario caused by benefit and cost of learning called Baldwin effect can guide evolution in the biology and artificial life. Therefore, we have been motivated... 

The digital radio receivers often have fast analog to digital converters delivering vast amount of data. However, in many cases, the signal of interest represents a small proportion of that bandwidth. A Digital Down Converter (DDC) is a filter that extracts the signal of interest from the incoming data stream. In this paper we first introduce an algorithm based on FFT which can be applied for simultaneous frequency shifting and decimating of Intermediate Frequency (IF) band signals, then a simplified iterative algorithm is suggested to improve the quality of reconstructed baseband signal. ©2007 IEEE  

Fast locking PLL-based wide-band frequency synthesizers used in high performance RF transceivers often require multi-band voltage controlled oscillator (VCO). These types of frequency synthesizers employ both discrete and continuous tuning mechanisms to satisfy wide frequency range and low VCO tuning gain simultaneously. To facilitate discrete tuning mechanisms, an auxiliary digital loop is required in order to select proper band of VCO. This digital loop is called adaptive frequency calibration (AFC). In this paper two methods of previous AFC architectures are discussed and improved to gain the minimum possible lock time of PLL. Then, these two methods are simulated and implemented over... 

A detection technique for extraction of total harmonics, individual harmonics, and reactive current components is introduced and its performance is evaluated. The detection algorithm is then adopted as part of the control system of a single-phase active power filter (APF) to provide the required signals for harmonic filtering and reactive power compensation. Performance of the overall system is evaluated based on digital time-domain simulation studies. The APF control system including the signal processing algorithms are implemented in Matlab/Simulink Fixed-Point Blockset to accommodate bit-length limitation which is a crucial factor in digital implementation. The power system including the...