Search for: digital-circuits
Article Microelectronic Engineering ; Volume 84, Issue 2 , 2007 , Pages 218-228 ; 01679317 (ISSN) ; Miremadi, S. G ; Ejlali, A ; Sharif University of Technology
This paper presents a method for functional verification of HDL models of digital circuits. The method is based on a co-operation between a simulator and an emulator and utilizes the advantages of both simulation-based and emulation-based verification to form a fast co-verification approach. This is done by verifying the intensive time-consuming part of the circuit in the emulator and the non-synthesizable part as well as the part of the circuit that needs intensive redesign process during the early steps of the design phase in the simulator. To demonstrate the co-verification approach, a tool was developed, which supports Verilog, VHDL, and mixed Verilog-VHDL models. Three benchmarks...
Article 2007 International Symposium on Integrated Circuits, ISIC, Singapore, 26 September 2007 through 28 September 2007 ; 2007 , Pages 5-8 ; 1424407974 (ISBN); 9781424407972 (ISBN) ; Ayatollahi, A ; Fakhraie, S. M ; Chahardori, M ; Sharif University of Technology
In search of low cost and flexible substrates organic transistors have been suggested as an alternate to silicon transistors. Level 1 model extraction, investigating different circuit styles and proposing two new circuit styles for organic integrated circuits is done in this paper. First, level 1 model of organic transistor is found using ID-VDS characteristics of transistors reported by . After that different design styles used in CMOS digital integrated circuits are reviewed and the functionality of these styles for organic integrated circuits is investigated. Two new circuit styles have been proposed in this section which have better performance for organic circuits comparing with...
Article 12th International Conference on Microelectronics, ICM 2000, 31 October 2000 through 2 November 2000 ; Volume 2000-October , 2000 , Pages 99-102 ; 9643600572 (ISBN) ; Atarodi, S. M ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc 2000
A novel cascode configuration previously presented as a high output resistance load (Fujimori and Sugimoto, 1998) has been investigated and utilized for amplification to achieve higher gain and bandwidth by the authors (Lofti and Atarodi, Proc. ICEE'00, vol.1, pp.83-8, 2000). A low-voltage single-stage opamp using this configuration is designed. Finally, based on this idea a 1.5-V offset- and gain-compensated 5th order switched-capacitor low pass filter with only 150 μA current consumption in a 0.8 μm process is designed. © 2000 IEEE
Article Journal of Superconductivity and Novel Magnetism ; Vol. 27, issue. 7 , 2014 , p. 1623-1628 ; Bozbey, A ; Fardmanesh, M ; Sharif University of Technology
Bi-directional RSFQ benefits from using both positive and negative SFQ pulses to manipulate and transfer digital data. This allows more flexibility in the design of simpler circuits with enhanced performance. On the other hand, using the AC bias current, one can replace on-chip resistive current distributors with inductors. This resembles RQL logic, but in contrast to RQL, it is possible to use the well-established standard RSFQ cells in bi-directional RSFQ. These two advantages (energy-efficient computation and flexibility in design) make bi-directional RSFQ a powerful tool in next-generation supercomputers and also compatible with ultra-low-temperature quantum computers. In this work, to...
Article Scientia Iranica ; Volume 14, Issue 6 , 2007 , Pages 566-570 ; 10263098 (ISSN) ; Sharif University of Technology
Sharif University of Technology 2007
The architecture of a hardwired simulator for implementation of a discrete event-driven simulation of digital systems at the logic level is presented. In the design of this system, attempts have been made to utilize techniques of high performance computing to have a system capable of simulating the digital circuits rapidly. The centralized event-driven simulation algorithm chosen here, has the advantages of being efficient and conceptually straightforward. The high reliability of the simulator has been taken care of through a collection of handshake signals between each two of the three main modules. © Sharif University of Technology, December 2007
Article 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design, Hyderabad, 3 January 2006 through 7 January 2006 ; Volume 2006 , 2006 , Pages 601-605 ; 10639667 (ISSN) ; 0769525024 (ISBN); 9780769525020 (ISBN) ; Emadi, M ; Farbiz, F ; Sharif University of Technology
A new level converter for use in dual voltage SOI digital circuits is presented. This technique uses the idea of keeper transistors, and consumes less power compared to the traditional methods. The effects of load capacitance on the circuit are studied by extensive simulations. © 2006 IEEE
Article 2008 IEEE Congress on Evolutionary Computation, CEC 2008, Hong Kong, 1 June 2008 through 6 June 2008 ; 2008 , Pages 2360-2364 ; 9781424418237 (ISBN) ; Jahangir, A. H ; Beigy, H ; Sharif University of Technology
Cartesian Genetic Programming (CGP) has an unusual genotype representation which makes it more efficient than Genetic programming (GP) in digital circuit design problem. However, to the best of our knowledge, all methods used in evolutionary design of digital circuits deal with rugged, complex search space, which results in long running time to obtain successful evolution. Therefore, employing a method to guide evolution in these spaces can facilitate achieving more reasonable results. It has been claimed that a two-step evolutionary scenario caused by benefit and cost of learning called Baldwin effect can guide evolution in the biology and artificial life. Therefore, we have been motivated...
Article Integration ; Volume 72 , May , 2020 , Pages 183-193 ; Safaei, B ; Ejlali, A ; Sharif University of Technology
Elsevier B.V 2020
With the emergence of various battery operated technologies in different computing domains and the challenge of heating in such technologies, the issue of energy dissipation has become more critical than ever before. In such systems, energy constraints in one hand, and heat generation, on the other hand, necessitates the employment of energy efficient technologies in the fabrication of digital circuits. One possible solution for mitigating the energy dissipation in digital circuits is the use of adiabatic families in the process of designing computing devices. Adiabatic circuits are designed mainly based on the principles of thermodynamics and provide a paradigm shift in the design of...
Article 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008, St. Julian's, 31 August 2008 through 3 September 2008 ; 2008 , Pages 21-24 ; 9781424421824 (ISBN) ; Zeinolabedinzadeh, S ; HajSadeghi, K ; Sharif University of Technology
Limitations in operation of analog switches at very low voltages have caused many problems in design of these types of switched capacitor circuits and data converters. In this paper by modifying a recently proposed clock boosting circuit, we could obtain a new structure with better performance for very low voltage circuits. This method requires simpler digital circuits in comparison with previously reported structures, as well as less number of transistors and smaller chip area. This method can be used for sampling the full swing signals with supply voltages as low as 0.4 volt. © 2008 IEEE
Reimbursing the handshake overhead of asynchronous circuits using compiler pre-synthesis optimizations, Article 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, DSD 2008, Parma, 3 September 2008 through 5 September 2008 ; 2008 , Pages 290-297 ; 9780769532776 (ISBN) ; Mirza Aghatabar, M ; Najibi, M ; Pedram, H ; Sadeghi, A ; Sharif University of Technology
Asynchronous circuits have many advantages vs synchronous design styles like high performance and lower power consumption; however, there is a drawback of big overhead in handshake circuitry of these circuits. In this paper, we have reduced the amount of these extra circuits by take advantage of some compiler techniques. The compiler methods can be used innovatively to improve the synthesis results in terms of both power consumption and area, since these code motions lead to removing of completion detection and validity check parts of asynchronous designs. To the best of our knowledge this is the first effort in using the compiler pre-synthesis optimizations in asynchronous circuits to...
Reduced complexity 1-bit high-order digital delta-sigma modulator for low-voltage fractional-N frequency synthesis applications, Article IEE Proceedings: Circuits, Devices and Systems ; Volume 152, Issue 5 , 2005 , Pages 471-477 ; 13502409 (ISSN) ; Afzali Kusha, A ; Dehghani, R ; Mehrara, M ; Atarodi, S. M ; Nourani, M ; Sharif University of Technology
A reduced complexity third-order digital delta-sigma modulator for fractional-N frequency synthesis is presented. The high-performance modulator, which consists of two subblocks, has a single-bit output making it best for this sort of application. A good shaping of quantisation noise is achieved using a new architecture for a digital third-order delta-sigma modulator. The hardware required for this modulator is considerably less than that in previously reported leading to lower power and area consumption and a higher operating frequency. The field programmable gate array (FPGA) implementation of the whole system shows an SNR of at least 94 dB and an operating input range of 0.7 of the full...
Soft error estimation and mitigation of digital circuits by characterizing input patterns of logic gates, Article Microelectronics Reliability ; Vol. 54, issue. 6-7 , 2014 , p. 1412-1420 ; Miremadi, S. G ; Asadi, H ; Fazeli, M ; Sharif University of Technology
Soft errors caused by particles strike in combinational parts of digital circuits are a major concern in the design of reliable circuits. Several techniques have been presented to protect combinational logic and reduce the overall circuit Soft Error Rate (SER). Such techniques, however, typically come at the cost of significant area and performance overheads. This paper presents a low area and zero-delay overhead method to protect digital circuits' combinational parts against particles strike. This method is made up of a combination of two sub-methods: (1) a SER estimation method based on signal probability, called Estimation by Characterizing Input Patterns (ECIP) and (2) a protection...
Article 2011 18th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2011, 11 December 2011 through 14 December 2011 ; December , 2011 , Pages 212-215 ; 9781457718458 (ISBN) ; Sharifkhani, M ; Gholami, M ; Sharif University of Technology
A low power 10 bit, 40 MS/s pipeline analog to digital converter is presented. A number of low-power techniques are proposed in various levels of abstraction. In circuit level, a low power class A/AB opamp with direct common-mode-feedback circuit (CMFB) is proposed which significantly reduces power in the opamps. In backend design, optimal series capacitors are layed out to break the deadlock between the mismatch and loading effect of the first stage capacitors. A customized software tool is developed based on the proposed opamp and architecture which provides optimum stage scaling factors, tail current and opamp transistor sizes. Simulations in 0.13um CMOS technology show that the ADC...
Article Proceedings - IEEE International Symposium on Circuits and Systems ; 2011 , Pages 514-517 ; 02714310 (ISSN) ; 9781424494736 (ISBN) ; Medi, A ; Sharif University of Technology
A new modeling and analysis of the nonlinearities caused by the capacitor mismatch errors in the pipeline analog-to-digital converters (ADCs) is presented. Error in each stage is modeled by an input-referred gain error and a nonlinear term. A method is proposed for calculation of the ADC integral nonlinearity (INL) from the total input referred error. Analytical expressions for estimation of the ADC INL in terms of standard deviation of random capacitor mismatch errors are derived. The proposed model is verified by system-level Monte Carlo simulations
A high power high voltage short pulse width pulse generator using direct drive method in application of modulating-cathode tubes drive, Article IEEE International Symposium on Industrial Electronics, 5 July 2009 through 8 July 2009 ; 2009 , Pages 2097-2102 ; 9781424443499 (ISBN) ; Sadriyeh, S. M. R ; Mohammadi, A ; Maghsoudlou, B ; Mokhtari, H ; Alizadeh, H. R ; Shams Mousavi, S. M ; Sharif University of Technology
The power supply of microwave tubes has high voltage and the possibility of produce high power pulse, which called in modulator. In this work, the results of design, construction and characterization of a direct drive pulse modulator for driving high power short pulse-width magnetron are reported. The sub-assemblies of modulator are; a primary high voltage supply, a switch bank with drivers and snubber circuits, a filament circuit, a digital control circuit with sensors and finally a pulse transformer. This paper is concerned with introduction and presentation of experimental evaluation of a new drive method for high power high voltage modulating-cathode microwave tubes. ©2009 IEEE