Sharif Digital Repository

A 6-bit passive phase shifter for S frequency band has been designed in a standard HEMT technology. A new switched-network topology has been proposed for implementing the 5.625 phase shift step which these digital bits are series with each other. We used Advanced Design System (ADS2010) to perform simulations. These digital bits will produce 64 different mode phase shift of -177.15 to +177.15 degree. In all cases simulation obtained less than 1 % error  

This paper presents the design of a 6-bit active digital phase shifter in 0.18-μm CMOS technology. The active phase shifter synthesizes the required phase using a phase interpolation process by adding quadrature phased input signals. It uses a new quadrature all-pass filter for quadrature signaling with a wide bandwidth and low phase error. The phase shifter has simulated RMS phase error of <0.85° at 2.4-5 GHz. The average voltage gain ranges from 1.7 dB at 2.4GHz to -0.14 dB at 5 GHz. Input P1 dB is typically 1.3±0.9 dBm at 3.5 GHz for overall phase states  

Usually the digital phase shifters are used to steer the beam of a phased array antenna, and the accuracy of beam steering and other properties of the radiation pattern is dependent on the number of bits of the phase shifter and its resolution. In this paper the results of simulations, accomplished using a number of phase feeding methods in order to reduce the phase quantization error effects are presented and three new methods are introduced and compared with the previous works. Copyright 2006 IEICE