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digital-to-analog
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Design of a Non-Bianry Analog to Digital Converterfor Impantable Neural Recording Microsystem
, M.Sc. Thesis Sharif University of Technology ; Sharifkhani, Mohammad (Supervisor) ; Sodagar, Amir Masoud (Supervisor)
Abstract
A new structure of implantable neural recording microsystem base on multiple valued logic (MVL) has been proposed. MVL is a new idea for reduction of occupied area and the power consumption of microelectronic. In another side, in implantable microsystems , occupied area and power consumption by this type of micro systems is a challenging problem in this field. Therefore, the problem of power consumption and occupied area can introduce as a prime stage of suggested microsystem completed design of convertor of analog to digital in usage of multiple level in this micro system worked. Design of convertor of analog to digital is a convertor of quaternary successive approximation. And also,...
A 1-V 400MS/s 14bit self-calibrated CMOS DAC with enhanced dynamic linearity
, Article 2004 IEEE International Symposium on Circuits and Systems - Proceedings, Vancouver, BC, 23 May 2004 through 26 May 2004 ; Volume 1 , 2004 , Pages I349-I352 ; 02714310 (ISSN) ; Mehrmanesh, S ; Atarodi, M ; Aslanzadeh, H. A ; Sharif University of Technology
2004
Abstract
A 1-V CMOS current steering digital to analog converter with enhanced static and dynamic linearity is presented. The 14-bit static linearity is achieved by a novel background analog self calibration technique which is suitable for low voltage applications and does not require error measurement and correction circuits. To improve dynamic linearity at high frequencies, a new low power track/attenuate output stage is used at the DAC output. Integral and differential nonlinearities of the proposed DAC corresponding, to 14-bit specification are less than 0.35LSB and 0.25LSB, respectively. The DAC is functional up to 400MS/S with SFDR better than 71dB in the Nyquist band. The circuit has been...
Circuit and Systematic Design of Low Power SAR ADC
, M.Sc. Thesis Sharif University of Technology ; Sharif Khani, Mohammad (Supervisor)
Abstract
Low power and high speed analog-to-digital converters (ADCs) are the key elements of communication and computing systems. There are several ADC structures such as delta-sigma, flash, pipeline, and successive approximation register (SAR) for different applications, albeit SAR ADCs are natural candidates of onchip designs for their low power and scalability benefits. Nowadays, SAR ADCs are widely being used in low-power moderate-resolution applications which need several tens of MS/s to low GS/s sampling rates. By virtue of the technology scaling power consumption of digital parts of a SAR ADC is reduced significantly. As a result, in a SAR ADC the power consumption of the digital-to-analog...
Zero-power mismatch-independent Digital to Analog converter
, Article Conference Proceedings - 13th IEEE International NEW Circuits and Systems Conference, NEWCAS 2015, 7 June 2015 through 10 June 2015 ; June , 2015 , Page(s): - 4 ; 9781479988938 (ISBN) ; Sendi, M. S. E ; Nikoofard, A ; Sharifkhani, M ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2015
Abstract
A new switched-capacitor Digital to Analog converter (DAC) is presented. In this method, a ladder of series capacitors is used to generate the output voltage levels. A correction phase is used to increase the precision of the DAC. It is analytically shown that the proposed DAC is mismatch and process independent by virtue of the correction phase. That is after some correction phases, the effect of mismatch on the reference voltage levels on the ladder diminishes and an accurate voltage division is provided. It is proven that the whole process sinks no extra charge from the power supply
A compact mixer and DAC for implementation of a direct conversion OQPSK transmitter
, Article 2007 IEEE Region 10 Conference, TENCON 2007, Taipei, 30 October 2007 through 2 November 2007 ; 2007 ; 1424412722 (ISBN); 9781424412723 (ISBN) ; Mehrmanesh, S ; Zamanlooy, B ; Atarodi, M ; Sharif University of Technology
2007
Abstract
A compact low power circuit for implementation of a direct conversion OQPSK modulator is proposed. The circuit consists of a digital to analog converter, a low pass filter and an up-converter mixer. By embedding these three blocks, the circuit performance is enhanced and the total power consumption is reduced. The mixer is designed base on a Gilbert cell with on chip inductor loads. Instead of transconductance transistors of Gilbert cell, a fully deferential current mode DAC is used and proficiently a low pass filter is embedded between them and therefore the linearity of total system is improved. All of circuits are designed based on 0.18 μm CMOS technology with a single 1.8 volt power...
Joint Source Channel Coding with Hybrid Digital Analog Codes in the Presence of Intereference
,
M.Sc. Thesis
Sharif University of Technology
;
Behroozi, Hamid
(Supervisor)
Abstract
In this thesis we consider transmitting an analog Gaussian source over an AWGN channel in the presence of an interference completely known at the transmitter intwo cases: 1) Compression bandwidth with interference uncorrelated with the sourceand 2) Matched bandwidth channel in the presence of interference correlated withthe source to be transmitted. We study joint source-channel coding schemes basedon hybrid digital-analog (HDA) codes. After providng a brief review, we will proposetwo new schemes for the ?rst case and one novel scheme for the second case. Aswe will see both schemes for the ?rst case achieve the optimal mean-squared error(MSE) distortion. The proposed HDA schemes can...
An ultra low-power digital to analog converter for SAR ADCs
, Article Proceedings of the International Conference on Microelectronics, ICM, 10 December 2017 through 13 December 2017 ; Volume 2017-December , 2018 , Pages 1-4 ; 9781538640494 (ISBN) ; Sharifkhani, M ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2018
Abstract
A new structure of Capacitive Digital to Analog Converters (CDAC) for SAR ADCs is presented. In this structure, a number of capacitors are used in different series configurations to generate desirable voltage levels based on an input binary code. the proposed CDAC consumes a certain amount of power regardless of the input code. This method achieves more than 99.9% power reduction and 98.9% area reduction compared to the conventional binary weighted CDAC. © 2017 IEEE
A novel design of hybrid-time-interleaved current steering digital to analog converter and its behavioral simulation considering non-ideal effects
, Article Integration ; Volume 69 , 2019 , Pages 321-334 ; 01679260 (ISSN) ; Torkzadeh, P ; Sadughi, S ; Sharif University of Technology
Elsevier B.V
2019
Abstract
This work presents a behavioral model for non-ideal effects in a novel Hybrid time-interleaved digital to analog converter (TIDAC). In Hybrid DACs, both ΔΣ and Nyquist structures are used. In this work, in the Nyquist path, the 2-time-interleaving technique is used and in the ΔΣ path, a new structure is proposed to reduce the critical path in the TI delta-sigma modulator (DSM). In conventional TIDSM, adding each channel to the structure leads to increasing the critical path as one full-adder. This, in turn, decreases the speed of modulator since a single feedback loop is utilized to compute the running sum of the input signals. In this work, a new type of poly-phase decomposition is...
A compact low power mixed-signal equalizer for gigabit ethernet applications
, Article ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Kos, 21 May 2006 through 24 May 2006 ; 2006 , Pages 5167-5170 ; 02714310 (ISSN); 0780393902 (ISBN); 9780780393905 (ISBN) ; Eghbalkhah, B ; Saeedi, S ; Afzali Kusha, A ; Atarodi, M ; Sharif University of Technology
2006
Abstract
In this paper we propose a novel structure of a discrete-time mixed-signal linear equalizer designed for analog front end of Gigabit Ethernet receivers. The circuit is an FIR filter which involves 6 taps based on a coefficient-rotating structure. Here, a simple structure is used for merging digital to analog conversion of the filter's coefficients and multipliers needed for 6 taps. This structure results in high speed and low power dissipation as well as less A/D converter complexity. Simulated in a 0.18 um CMOS technology, this equalizer operates at 125 MHz while dissipating 10 mw from a 1.8 V power supply. © 2006 IEEE
A low voltage 14-bit self-calibrated CMOS DAC with enhanced dynamic linearity
, Article Analog Integrated Circuits and Signal Processing ; Volume 43, Issue 2 , 2005 , Pages 137-145 ; 09251030 (ISSN) ; Mehrmanesh, S ; Atarodi, M ; Sharif University of Technology
2005
Abstract
A 1-V CMOS current steering digital to analog converter with enhanced static and dynamic linearity is presented. The 14-bit static linearity is achieved by a background analog self calibration technique which is suitable for low voltage applications and does not require error measurement and correction circuits. To improve dynamic linearity at high frequencies a track/attenuate output stage is used at the DAC output. Integral and differential nonlinearities of the proposed DAC corresponding to 14-bit specification are less than 0.35 and 0.25 LSB respectively. The DAC is functional up to 400MS/s with SFDR better than 71 dB in the Nyquist band. The circuit has been designed and simulated in a...
A 2-GHz CMOS image-reject receiver with LMS calibration
, Article IEEE Journal of Solid-State Circuits ; Volume 38, Issue 2 , 2003 , Pages 167-175 ; 00189200 (ISSN) ; Razavi, B ; Sharif University of Technology
2003
Abstract
This paper describes a sign-sign least-mean squares (LMS) technique to calibrate gain and phase errors in the signal path of a Weaver image-reject receiver. The calibration occurs at startup and the results are stored digitally, allowing continuous signal reception thereafter. Fabricated in a standard digital 0.25-μm CMOS technology, the receiver achieves an image-rejection ratio of 57 dB after calibration, a noise figure of 5.2 dB, and a third-order input intercept point of -17 dBm. The circuit consumes 55 mW in calibration mode and 50 mW in normal receiver mode from a 2.5-V power supply. The prototype occupies an area of 1.23 × 1.84 mm2
Analysis of C-2C DAC Mismatch Effects in SAR ADCs
, M.Sc. Thesis Sharif University of Technology ; Sharif Khani, Mohammad (Supervisor)
Abstract
Analog to digital converters is one of the main building blocks of today's circuits. These circuits play an important role in signal processing. Since these circuits consist of analog and digital sections, a large percentage of the power consumed in a circuit is allocated to this section. Therefore, in applications such as medical devices, wearable applications and wireless technology where power control is very important and necessary, reducing the power of analog to digital converters is very important. One of the simplest analog-to-digital converters from the design point of view is Successive Approximation Register (SAR) analog-to-digital converters. This type of analog-to-digital...
A fully linear 5.2 GHz - 5.8 GHz digitally controlled oscillator in 65-nm CMOS technology
, Article Microelectronics Journal ; Volume 90 , 2019 , Pages 48-57 ; 00262692 (ISSN) ; Torkzadeh, P ; Sadughi, S ; Sharif University of Technology
Elsevier Ltd
2019
Abstract
A low-power fully linear integrated CMOS LC-based Digitally Controlled Oscillator is presented. The DCO operates in 5.2 GHz to 5.8 GHz range for using in IEEE 802.11a wireless applications. The system has been designed using 65 nm CMOS technology and 1.2 V supply voltage. By applying a proposed filter in DCO architecture −133.41 dBc/Hz phase noise at 1 MHz offset frequency from the fundamental carrier is achieved. The code generator and digital to analog converter designed to provide the high precision voltage required for fine-tuning. The output frequency swept through 10 control bits with 100 KHz resolution. The measured RMS jitter (∑ [1 KHz – 2 GHz]) from 5.8 GHz carrier is 1.65 fs. The...
5-6 GHz dual-vector phase shifter in 0.18 μm LID CMOS
, Article 27th Iranian Conference on Electrical Engineering, ICEE 2019, 30 April 2019 through 2 May 2019 ; 2019 , Pages 82-86 ; 9781728115085 (ISBN) ; Fakharzadeh, M ; Safarian, A ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2019
Abstract
In this paper, a low power active phase shifter in 0.18 μm CMOS technology, operating from 5 to 6 GHz, for WLAN applications is presented. Design equations for this novel structure, which consists of two current steering stages, transconductance stage and DACs, are derived, thoroughly. This phase shifter has a range of 360° with 5.625° phase resolution. The power consumption is 35 mW. The RMS phase error is only 0.3°. The simulated power gain, input P1dB, and NF are 4 dB, -0.8 dBm and 6 dB, respectively
Circuit & Systematic Design of Low Power & High Speed SAR ADC
, M.Sc. Thesis Sharif University of Technology ; Sharifkhani, Mohammad (Supervisor)
Abstract
SAR ADC is a data converter which is based on binary search to convert an analog signal to a digital signal. Unlike other converters like pipeline, most of its constituent parts are digital, and hence scalable with process and consume less power, moreover can have better speed and power performance. With advanced technologies, namely 45nm and 32 nm CMOS, SAR ADCs are preferable as they consume much less power and area, therefore well-suited for portable applications, as opposed to Flash and Pipleline converters.
The main drawback of this type of converter is its limited speed which is due to the fact that one clock cycle is required to evaluate each bit. As a result, there is a...
The main drawback of this type of converter is its limited speed which is due to the fact that one clock cycle is required to evaluate each bit. As a result, there is a...
On the transmission of a Laplacian source over an AWLN channel with bandwidth compression
, Article 2012 6th International Symposium on Telecommunications, IST 2012 ; 2012 , Pages 669-673 ; 9781467320733 (ISBN) ; Aghagolzadeh, A ; Behroozi, H ; Sharif University of Technology
2012
Abstract
We study transmission of a memoryless Laplacian source over an average-power limited additive white Laplacian noise (AWLN) channel under bandwidth compression in two cases: 1) matched signal-to-noise ratio (SNR), 2) mismatched SNR. A hybrid digital-analog (HDA) joint source-channel coding (JSCC) scheme is proposed and show that this scheme can achieve a distortion very close to the lower bound on mean-absolute error (MAE) distortion under matched SNR conditions
Zero-power mismatch-independent digital to analog converter
, Article AEU - International Journal of Electronics and Communications ; Volume 69, Issue 11 , 2015 , Pages 1599-1605 ; 14348411 (ISSN) ; Sharifkhani, M ; Sharif University of Technology
Elsevier GmbH
2015
Abstract
A new switched-capacitor digital to analog converter (DAC) is presented. In this DAC, a ladder of series capacitors is used to generate the output voltage levels. A correction phase is used to increase the precision of the DAC. It is analytically shown that the proposed DAC is mismatch independent by virtue of the correction phase. That is after few correction phases (typically one), the effect of mismatch on the reference voltage levels on the ladder diminishes and an accurate voltage division is provided. It is proven that the whole process sinks no extra charge from the power supply. Furthermore, post layout simulations in 0.18 μm technology proves the benefits of the proposed method
A noise shaped flash time to digital converter for all digital frequency synthesizers
, Article ECCTD 2009 - European Conference on Circuit Theory and Design Conference Program, 23 August 2009 through 27 August 2009 ; 2009 , Pages 898-901 ; 9781424438969 (ISBN) ; Atarodi, M ; Sharif University of Technology
Abstract
Reduction of Time to Digital Converter (TDC) quantization related phase noise is one of the most important challenges in all digital frequency synthesizer design. In this paper, a new structure is proposed to shape the quantization noise of flash TDCs. To verify effectiveness of the proposed general noise shaping technique, it is employed on a single delay chain flash TDC. To compensate the process variation effects on the implemented circuits, a calibration technique is also proposed. The design is implemented in 0.18μm CMOS technology. Simulations show effective noise shaping of output quantization noise
An accurate low-power DAC for SAR ADCs
, Article 59th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2016, 16 October 2016 through 19 October 2016 ; 2017 ; 15483746 (ISSN); 9781509009169 (ISBN) ; Khorami, A ; Sharifkhani, M ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2017
Abstract
A highly energy-efficiency switching procedure for the capacitor-splitting digital-To-Analog converter (DAC) is presented for successive approximation register (SAR) analogue-To-digital converters (ADCs). In this procedure, the MSB capacitor is divided into its binary constituents. All output digital bits, except the least significant bit (LSB), is determined using reference voltage (Vref), while the common-mode voltage (Vcm) is used to determine the LSB. Therefore, the precision of the proposed SAR ADC is independent of the precision of Vcm except in the LSB. This method reduces the area by 75% compared to the conventional binary weighted DAC and reduces the switching energy by 96.89%. ©...
Design and implementation of a stable platform digital controller based on DSP
, Article ICSES 2008 International Conference on Signals and Electronic Systems, ICSES'08, Krakow, 14 September 2008 through 17 September 2008 ; 2008 , Pages 453-456 ; 9788388309526 (ISBN) ; Chamani Takaldani, H. R ; Moosavienia, A ; Monfaredi, K ; Ebrahimi Atani, R ; Sharif University of Technology
2008
Abstract
The principle, configuration, and the special features of a stable platform digital controller are presented in this paper. The main goal of this paper is replacing an analog controller with its awaiting digital one. This has been done using TMS320LF2402 digital signal processor which offers the enhanced TMS320 DSP architectural design of the C2xx core CPU for low-cost, low-power, and high-performance processing capabilities. The experimental results show that the digital controller is identical to the analog one and can be a suitable replacement for the analog controller. Copyright © 2008 by Department of Electronics, AGH University of Science and Technology