Search for: digital-to-analog
Total 24 records
M.Sc. Thesis Sharif University of Technology ; Sharifkhani, Mohammad ; Sodagar, Amir Masoud
A new structure of implantable neural recording microsystem base on multiple valued logic (MVL) has been proposed. MVL is a new idea for reduction of occupied area and the power consumption of microelectronic. In another side, in implantable microsystems , occupied area and power consumption by this type of micro systems is a challenging problem in this field. Therefore, the problem of power consumption and occupied area can introduce as a prime stage of suggested microsystem completed design of convertor of analog to digital in usage of multiple level in this micro system worked. Design of convertor of analog to digital is a convertor of quaternary successive approximation. And also,...
M.Sc. Thesis Sharif University of Technology ; Sharif Khani, Mohammad
Low power and high speed analog-to-digital converters (ADCs) are the key elements of communication and computing systems. There are several ADC structures such as delta-sigma, flash, pipeline, and successive approximation register (SAR) for different applications, albeit SAR ADCs are natural candidates of onchip designs for their low power and scalability benefits. Nowadays, SAR ADCs are widely being used in low-power moderate-resolution applications which need several tens of MS/s to low GS/s sampling rates. By virtue of the technology scaling power consumption of digital parts of a SAR ADC is reduced significantly. As a result, in a SAR ADC the power consumption of the digital-to-analog...
Article Conference Proceedings - 13th IEEE International NEW Circuits and Systems Conference, NEWCAS 2015, 7 June 2015 through 10 June 2015 ; June , 2015 , Page(s): - 4 ; 9781479988938 (ISBN) ; Sendi, M. S. E ; Nikoofard, A ; Sharifkhani, M ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc 2015
A new switched-capacitor Digital to Analog converter (DAC) is presented. In this method, a ladder of series capacitors is used to generate the output voltage levels. A correction phase is used to increase the precision of the DAC. It is analytically shown that the proposed DAC is mismatch and process independent by virtue of the correction phase. That is after some correction phases, the effect of mismatch on the reference voltage levels on the ladder diminishes and an accurate voltage division is provided. It is proven that the whole process sinks no extra charge from the power supply
Article 2007 IEEE Region 10 Conference, TENCON 2007, Taipei, 30 October 2007 through 2 November 2007 ; 2007 ; 1424412722 (ISBN); 9781424412723 (ISBN) ; Mehrmanesh, S ; Zamanlooy, B ; Atarodi, M ; Sharif University of Technology
A compact low power circuit for implementation of a direct conversion OQPSK modulator is proposed. The circuit consists of a digital to analog converter, a low pass filter and an up-converter mixer. By embedding these three blocks, the circuit performance is enhanced and the total power consumption is reduced. The mixer is designed base on a Gilbert cell with on chip inductor loads. Instead of transconductance transistors of Gilbert cell, a fully deferential current mode DAC is used and proficiently a low pass filter is embedded between them and therefore the linearity of total system is improved. All of circuits are designed based on 0.18 μm CMOS technology with a single 1.8 volt power...
M.Sc. Thesis Sharif University of Technology ; Behroozi, Hamid
In this thesis we consider transmitting an analog Gaussian source over an AWGN channel in the presence of an interference completely known at the transmitter intwo cases: 1) Compression bandwidth with interference uncorrelated with the sourceand 2) Matched bandwidth channel in the presence of interference correlated withthe source to be transmitted. We study joint source-channel coding schemes basedon hybrid digital-analog (HDA) codes. After providng a brief review, we will proposetwo new schemes for the ?rst case and one novel scheme for the second case. Aswe will see both schemes for the ?rst case achieve the optimal mean-squared error(MSE) distortion. The proposed HDA schemes can...
Article Proceedings of the International Conference on Microelectronics, ICM, 10 December 2017 through 13 December 2017 ; Volume 2017-December , 2018 , Pages 1-4 ; 9781538640494 (ISBN) ; Sharifkhani, M ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc 2018
A new structure of Capacitive Digital to Analog Converters (CDAC) for SAR ADCs is presented. In this structure, a number of capacitors are used in different series configurations to generate desirable voltage levels based on an input binary code. the proposed CDAC consumes a certain amount of power regardless of the input code. This method achieves more than 99.9% power reduction and 98.9% area reduction compared to the conventional binary weighted CDAC. © 2017 IEEE
A novel design of hybrid-time-interleaved current steering digital to analog converter and its behavioral simulation considering non-ideal effects, Article Integration ; Volume 69 , 2019 , Pages 321-334 ; 01679260 (ISSN) ; Torkzadeh, P ; Sadughi, S ; Sharif University of Technology
Elsevier B.V 2019
This work presents a behavioral model for non-ideal effects in a novel Hybrid time-interleaved digital to analog converter (TIDAC). In Hybrid DACs, both ΔΣ and Nyquist structures are used. In this work, in the Nyquist path, the 2-time-interleaving technique is used and in the ΔΣ path, a new structure is proposed to reduce the critical path in the TI delta-sigma modulator (DSM). In conventional TIDSM, adding each channel to the structure leads to increasing the critical path as one full-adder. This, in turn, decreases the speed of modulator since a single feedback loop is utilized to compute the running sum of the input signals. In this work, a new type of poly-phase decomposition is...
Article Microelectronics Journal ; Volume 90 , 2019 , Pages 48-57 ; 00262692 (ISSN) ; Torkzadeh, P ; Sadughi, S ; Sharif University of Technology
Elsevier Ltd 2019
A low-power fully linear integrated CMOS LC-based Digitally Controlled Oscillator is presented. The DCO operates in 5.2 GHz to 5.8 GHz range for using in IEEE 802.11a wireless applications. The system has been designed using 65 nm CMOS technology and 1.2 V supply voltage. By applying a proposed filter in DCO architecture −133.41 dBc/Hz phase noise at 1 MHz offset frequency from the fundamental carrier is achieved. The code generator and digital to analog converter designed to provide the high precision voltage required for fine-tuning. The output frequency swept through 10 control bits with 100 KHz resolution. The measured RMS jitter (∑ [1 KHz – 2 GHz]) from 5.8 GHz carrier is 1.65 fs. The...
Article 27th Iranian Conference on Electrical Engineering, ICEE 2019, 30 April 2019 through 2 May 2019 ; 2019 , Pages 82-86 ; 9781728115085 (ISBN) ; Fakharzadeh, M ; Safarian, A ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc 2019
In this paper, a low power active phase shifter in 0.18 μm CMOS technology, operating from 5 to 6 GHz, for WLAN applications is presented. Design equations for this novel structure, which consists of two current steering stages, transconductance stage and DACs, are derived, thoroughly. This phase shifter has a range of 360° with 5.625° phase resolution. The power consumption is 35 mW. The RMS phase error is only 0.3°. The simulated power gain, input P1dB, and NF are 4 dB, -0.8 dBm and 6 dB, respectively
M.Sc. Thesis Sharif University of Technology ; Sharifkhani, Mohammad
SAR ADC is a data converter which is based on binary search to convert an analog signal to a digital signal. Unlike other converters like pipeline, most of its constituent parts are digital, and hence scalable with process and consume less power, moreover can have better speed and power performance. With advanced technologies, namely 45nm and 32 nm CMOS, SAR ADCs are preferable as they consume much less power and area, therefore well-suited for portable applications, as opposed to Flash and Pipleline converters.
The main drawback of this type of converter is its limited speed which is due to the fact that one clock cycle is required to evaluate each bit. As a result, there is a...
The main drawback of this type of converter is its limited speed which is due to the fact that one clock cycle is required to evaluate each bit. As a result, there is a...
Article 2012 6th International Symposium on Telecommunications, IST 2012 ; 2012 , Pages 669-673 ; 9781467320733 (ISBN) ; Aghagolzadeh, A ; Behroozi, H ; Sharif University of Technology
We study transmission of a memoryless Laplacian source over an average-power limited additive white Laplacian noise (AWLN) channel under bandwidth compression in two cases: 1) matched signal-to-noise ratio (SNR), 2) mismatched SNR. A hybrid digital-analog (HDA) joint source-channel coding (JSCC) scheme is proposed and show that this scheme can achieve a distortion very close to the lower bound on mean-absolute error (MAE) distortion under matched SNR conditions
Article AEU - International Journal of Electronics and Communications ; Volume 69, Issue 11 , 2015 , Pages 1599-1605 ; 14348411 (ISSN) ; Sharifkhani, M ; Sharif University of Technology
Elsevier GmbH 2015
A new switched-capacitor digital to analog converter (DAC) is presented. In this DAC, a ladder of series capacitors is used to generate the output voltage levels. A correction phase is used to increase the precision of the DAC. It is analytically shown that the proposed DAC is mismatch independent by virtue of the correction phase. That is after few correction phases (typically one), the effect of mismatch on the reference voltage levels on the ladder diminishes and an accurate voltage division is provided. It is proven that the whole process sinks no extra charge from the power supply. Furthermore, post layout simulations in 0.18 μm technology proves the benefits of the proposed method
Article ECCTD 2009 - European Conference on Circuit Theory and Design Conference Program, 23 August 2009 through 27 August 2009 ; 2009 , Pages 898-901 ; 9781424438969 (ISBN) ; Atarodi, M ; Sharif University of Technology
Reduction of Time to Digital Converter (TDC) quantization related phase noise is one of the most important challenges in all digital frequency synthesizer design. In this paper, a new structure is proposed to shape the quantization noise of flash TDCs. To verify effectiveness of the proposed general noise shaping technique, it is employed on a single delay chain flash TDC. To compensate the process variation effects on the implemented circuits, a calibration technique is also proposed. The design is implemented in 0.18μm CMOS technology. Simulations show effective noise shaping of output quantization noise
Article 59th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2016, 16 October 2016 through 19 October 2016 ; 2017 ; 15483746 (ISSN); 9781509009169 (ISBN) ; Khorami, A ; Sharifkhani, M ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc 2017
A highly energy-efficiency switching procedure for the capacitor-splitting digital-To-Analog converter (DAC) is presented for successive approximation register (SAR) analogue-To-digital converters (ADCs). In this procedure, the MSB capacitor is divided into its binary constituents. All output digital bits, except the least significant bit (LSB), is determined using reference voltage (Vref), while the common-mode voltage (Vcm) is used to determine the LSB. Therefore, the precision of the proposed SAR ADC is independent of the precision of Vcm except in the LSB. This method reduces the area by 75% compared to the conventional binary weighted DAC and reduces the switching energy by 96.89%. ©...
Article ICSES 2008 International Conference on Signals and Electronic Systems, ICSES'08, Krakow, 14 September 2008 through 17 September 2008 ; 2008 , Pages 453-456 ; 9788388309526 (ISBN) ; Chamani Takaldani, H. R ; Moosavienia, A ; Monfaredi, K ; Ebrahimi Atani, R ; Sharif University of Technology
The principle, configuration, and the special features of a stable platform digital controller are presented in this paper. The main goal of this paper is replacing an analog controller with its awaiting digital one. This has been done using TMS320LF2402 digital signal processor which offers the enhanced TMS320 DSP architectural design of the C2xx core CPU for low-cost, low-power, and high-performance processing capabilities. The experimental results show that the digital controller is identical to the analog one and can be a suitable replacement for the analog controller. Copyright © 2008 by Department of Electronics, AGH University of Science and Technology
Efficient Circuit and Systematic Design of Successive Approximation Register Analog to Digital Converters, Ph.D. Dissertation Sharif University of Technology ; Sharifkhani, Mohammad
Successive Approximation Register (SAR) Analog to Digital Converter (ADC) converts an analog signal to a digital code based on binary search. In contrast to other converters, such as Pipeline and Flash ADCs, most of the SAR ADC components are digital, hence, SAR ADC is technology scalable. Therefore, designed using smaller tehcnologies, SAR ADCs are able to operate at a higher frequency with a lower power consumption and area. The main focus of this thesis is to reduce power consumption, although the proposed techniques and circuits are able to improve other features such as precision, area, or speed.Considering Digital to Analog Converter (DAC), a low-power structure and a novel method to...
Article IEEE Transactions on Communications ; Vol. 62, issue. 7 , 2014 , p. 2544-2557 ; Aghagolzadeh, A ; Behroozi, H ; Sharif University of Technology
In this paper, we study transmission of a memoryless Laplacian source over three types of channels: additive white Laplacian noise (AWLN), additive white Gaussian noise (AWGN), and slow flat-fading Rayleigh channels under both bandwidth compression and bandwidth expansion. For this purpose, we analyze two well-known hybrid digital-analog (HDA) joint source-channel coding schemes for bandwidth compression and one for bandwidth expansion. Then we obtain achievable (absolute-error) distortion regions of the HDA schemes for the matched signal-to-noise ratio (SNR) case as well as the mismatched SNR scenario. Using numerical examples, it is shown that these schemes can achieve a distortion very...
Article ICIAS 2012 - 2012 4th International Conference on Intelligent and Advanced Systems: A Conference of World Engineering, Science and Technology Congress (ESTCON) - Conference Proceedings, 12 June 2012 through 14 June 2012 ; Volume 2 , June , 2012 , Pages 725-728 ; 9781457719677 (ISBN) ; Aghdam, E. N ; Najafi, V ; Sharif University of Technology
A Multi-level asynchronous delta sigma modulator consist of several Schmitt-triggers and a novel time-to-digital converter is presented as a core of a delta sigma modulation based analog to digital converter (ADC). The modulator firstly modulates the amplitude of its analog input signal to a multilevel asynchronous duty-cycle modulated signal. Then a time to digital converter (TDC) must be applied to generate digital representation of the received signal from the multi-level asynchronous duty-cycle modulated signal. A multi-level structure has been developed in this work while the prior works often used a single Schmitt. One of the most important limitations in conventional asynchronous...
Optimal HDA schemes for transmission of a Gaussian source over a Gaussian channel with bandwidth compression in the presence of an interference, Article IEEE Transactions on Signal Processing ; Volume 60, Issue 4 , January , 2012 , Pages 2081-2085 ; 1053587X (ISSN) ; Behroozi, H ; Sharif University of Technology
We consider transmission of a Gaussian source over a Gaussian channel under bandwidth compression in the presence of an interference known only to the transmitter. We study hybrid digital-analog (HDA) joint source-channel coding schemes and propose two novel layered coding schemes that achieve the optimal mean-squared error (MSE) distortion. This can be viewed as the extension of results by Wilson ["Joint Source Channel Coding With Side Information Using Hybrid Digital Analog Codes," IEEE Trans. Inf. Theory, vol. 56, no. 10, pp. 4922-2940, Oct. 2010], originally proposed for sending a Gaussian source over a Gaussian channel in two cases: 1) Matched bandwidth with known interference only at...
Optimal HDA codes for sending a Gaussian source over a Gaussian channel with bandwidth compression in the presence of an interference, Article 2011 IEEE Information Theory Workshop, ITW 2011 ; 2011 , Pages 325-329 ; 9781457704376 (ISBN) ; Behroozi, H ; Sharif University of Technology
In this paper, we consider transmission of a Gaussian source over a Gaussian channel under bandwidth compression in the presence of interference known only to the transmitter. We study hybrid digital-analog (HDA) joint source-channel coding schemes and propose two novel coding schemes that achieve the optimal mean-squared error (MSE) distortion. This can be viewed as the extension of results by Wilson et al. , originally proposed for sending a Gaussian source over a Gaussian channel in two cases: 1) Matched bandwidth with known interference only at the transmitter, 2) bandwidth compression where there is no interference in the channel. The proposed HDA codes can cancel the interference of...