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digital-to-analog-converter--dac
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A 1-V 400MS/s 14bit self-calibrated CMOS DAC with enhanced dynamic linearity
, Article 2004 IEEE International Symposium on Circuits and Systems - Proceedings, Vancouver, BC, 23 May 2004 through 26 May 2004 ; Volume 1 , 2004 , Pages I349-I352 ; 02714310 (ISSN) ; Mehrmanesh, S ; Atarodi, M ; Aslanzadeh, H. A ; Sharif University of Technology
2004
Abstract
A 1-V CMOS current steering digital to analog converter with enhanced static and dynamic linearity is presented. The 14-bit static linearity is achieved by a novel background analog self calibration technique which is suitable for low voltage applications and does not require error measurement and correction circuits. To improve dynamic linearity at high frequencies, a new low power track/attenuate output stage is used at the DAC output. Integral and differential nonlinearities of the proposed DAC corresponding, to 14-bit specification are less than 0.35LSB and 0.25LSB, respectively. The DAC is functional up to 400MS/S with SFDR better than 71dB in the Nyquist band. The circuit has been...
5-6 GHz dual-vector phase shifter in 0.18 μm LID CMOS
, Article 27th Iranian Conference on Electrical Engineering, ICEE 2019, 30 April 2019 through 2 May 2019 ; 2019 , Pages 82-86 ; 9781728115085 (ISBN) ; Fakharzadeh, M ; Safarian, A ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2019
Abstract
In this paper, a low power active phase shifter in 0.18 μm CMOS technology, operating from 5 to 6 GHz, for WLAN applications is presented. Design equations for this novel structure, which consists of two current steering stages, transconductance stage and DACs, are derived, thoroughly. This phase shifter has a range of 360° with 5.625° phase resolution. The power consumption is 35 mW. The RMS phase error is only 0.3°. The simulated power gain, input P1dB, and NF are 4 dB, -0.8 dBm and 6 dB, respectively