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Thermal noise analysis of multi-bit SC gain-stages for low-voltage high-resolution pipeline ADC design
, Article International Symposium on Signals, Circuits and Systems, SCS 2003, 10 July 2003 through 11 July 2003 ; Volume 2 , 2003 , Pages 581-584 ; 0780379799 (ISBN); 9780780379794 (ISBN) ; Saeedfär, A ; Hoseini, H. Z ; Shoaei, O ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2003
Abstract
Analysis of thermal noise in switched-capacitor multi-bit gain-stages used in low-voltage high-resolution pipeline analog-to-digital converters is presented. The analytical expression obtained for the input referred noise power, which should be considered in the design procedure, is general for any number of bits being resolved and shows that the noise power is decreased when more bits are resolved in the stage. © 2003 IEEE
Exploration of process and competitive factors of entrepreneurship in digital space: A multiple case study in Iran
, Article Education, Business and Society: Contemporary Middle Eastern Issues ; Volume 4, Issue 4 , 2011 , Pages 267-279 ; 17537983 (ISSN) ; Akhavan, P ; Eshraghian, F ; Sharif University of Technology
2011
Abstract
Purpose: The purpose of this paper is to explore the process and competitive factors of entrepreneurship in digital space in Iran. Design/methodology/approach: In the last decades, the development and advancement of information and communication technologies (ICTs) and the business innovations related to them have defined a new economy which is known as "digital economy". Establishing and running businesses in this digital space means carrying out a kind of electronic commerce by exploiting the internet and other electronic networks. The new digital economy provides exceptional opportunities for many entrepreneurs to create new ventures in different business areas according to electronic...
Investigating different circuit styles for digital circuits using organic transistors
, Article 2007 International Symposium on Integrated Circuits, ISIC, Singapore, 26 September 2007 through 28 September 2007 ; 2007 , Pages 5-8 ; 1424407974 (ISBN); 9781424407972 (ISBN) ; Ayatollahi, A ; Fakhraie, S. M ; Chahardori, M ; Sharif University of Technology
2007
Abstract
In search of low cost and flexible substrates organic transistors have been suggested as an alternate to silicon transistors. Level 1 model extraction, investigating different circuit styles and proposing two new circuit styles for organic integrated circuits is done in this paper. First, level 1 model of organic transistor is found using ID-VDS characteristics of transistors reported by [9]. After that different design styles used in CMOS digital integrated circuits are reviewed and the functionality of these styles for organic integrated circuits is investigated. Two new circuit styles have been proposed in this section which have better performance for organic circuits comparing with...
Collaborative digital library: enhancing digital collections to improve learning in educational programs
, Article Proceeding JCDL '09 Proceedings of the 9th ACM/IEEE-CS joint conference on Digital libraries Pages 359-360 ; 2009 , Pages 359- 360 ; 15525996 (ISSN); 9781605586977 (ISBN) ; Dehghani Firouzabadi, A ; Khalkhali, I ; Afzali, H. R ; Ashurzad Delcheh, M ; Shoja Shafiei, M ; Alipour, M ; ACM SIGWEB; ACM SIGIR; IEEE CS ; Sharif University of Technology
2009
Abstract
In this article, a universal collaborative and competitive approach is introduced for deployment of digital collections in an ideal Digital Library (DL) for future's educational system. The collaborative and open-source aspects of the system guarantee its growth and the competitive aspects guarantee the accuracy
Design and implementation of a stable platform digital controller based on DSP
, Article ICSES 2008 International Conference on Signals and Electronic Systems, ICSES'08, Krakow, 14 September 2008 through 17 September 2008 ; 2008 , Pages 453-456 ; 9788388309526 (ISBN) ; Chamani Takaldani, H. R ; Moosavienia, A ; Monfaredi, K ; Ebrahimi Atani, R ; Sharif University of Technology
2008
Abstract
The principle, configuration, and the special features of a stable platform digital controller are presented in this paper. The main goal of this paper is replacing an analog controller with its awaiting digital one. This has been done using TMS320LF2402 digital signal processor which offers the enhanced TMS320 DSP architectural design of the C2xx core CPU for low-cost, low-power, and high-performance processing capabilities. The experimental results show that the digital controller is identical to the analog one and can be a suitable replacement for the analog controller. Copyright © 2008 by Department of Electronics, AGH University of Science and Technology
Design and optimization of fully digital SQUID based on bi-directional RSFQ
, Article Journal of Superconductivity and Novel Magnetism ; Vol. 27, issue. 7 , 2014 , p. 1623-1628 ; Bozbey, A ; Fardmanesh, M ; Sharif University of Technology
Abstract
Bi-directional RSFQ benefits from using both positive and negative SFQ pulses to manipulate and transfer digital data. This allows more flexibility in the design of simpler circuits with enhanced performance. On the other hand, using the AC bias current, one can replace on-chip resistive current distributors with inductors. This resembles RQL logic, but in contrast to RQL, it is possible to use the well-established standard RSFQ cells in bi-directional RSFQ. These two advantages (energy-efficient computation and flexibility in design) make bi-directional RSFQ a powerful tool in next-generation supercomputers and also compatible with ultra-low-temperature quantum computers. In this work, to...
Designing a collaborative digital library to improve educational systems accompanied by a perspective from Iranian scholar attitudes
, Article International Conference on Enterprise Information Systems and Web Technologies 2010, EISWT 2010, 12 July 2010 through 14 July 2010 ; 2010 , Pages 132-140 ; 9781617820656 (ISBN) ; Firouz Abadi, A. D ; Khalkhali, I ; Shafiei, M. S ; Vojdanijahromi, R ; Sharif University of Technology
Abstract
In this article, a universal collaborative and competitive approach is introduced for deployment of digital collections in an ideal Digital Library for future's educational system. A hierarchical structure is proposed to be used for browsing and searching within mass of digital contents provided for union of curriculums worldwide. The collaborative and open-source aspects of the system guarantee the growth of the Digital Library. On the other hand, the competitive and reviewing aspects guarantee the accuracy of the novel library contents. Two experiments confirm the need for such a universal Digital Library worldwide to enhance learning capabilities, increase accessibility, avoid redundancy...
Design of low power comparator-reduced hybrid ADC
, Article Microelectronics Journal ; Volume 79 , 2018 , Pages 79-90 ; 00262692 (ISSN) ; Hajsadeghi, K ; Khorami, A ; Sharif University of Technology
Elsevier Ltd
2018
Abstract
This paper presents a new low-power comparator-reduced hybrid ADC. The proposed ADC uses dynamic comparators to perform a high-speed low-power conversion. In order to reduce the offset and kickback noise effect of conventional dynamic comparators, a new low-kickback noise comparator with a high pre-amplifier gain is presented. Two 4bit and 8bit ADCs are designed and simulated in 0.18 μm CMOS technology with 1.8 v supply voltage. INL and DNL of 4bit ADC are less than 0.4LSB and 0.5LSB, respectively, while 8bit ADC obtains DNL and INL of 0.83LSB and 1.3LSB, respectively. With ENOB of 3.6bit and 7.2bit for 4bit and 8bit ADCs, the 4bit ADC consumes only 1.7 mW at the sampling rate of 400 Ms/s...
A low-power comparator-reduced flash ADC using dynamic comparators
, Article 24th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2017, 5 December 2017 through 8 December 2017 ; Volume 2018-January , 2018 , Pages 5-8 ; 9781538619117 (ISBN) ; Hajsadeghi, K ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2018
Abstract
This paper presents a new low-power reduced comparator flash ADC. The proposed ADC uses dynamic comparators to perform a high-speed low-power conversion. In order to reduce offset and kick-back noise effect of conventional dynamic comparators, a new comparator with a higher pre-amplifier gain along with the mathematical analysis is presented. The proposed 4bit ADC is simulated in 0.18um with 1.8-υ supply voltage. SNDR and SFDR of the ADC are 23dB and 26.5dB, respectively. The ADC consumes only 0.95mw at the sampling rate of 400MS/s. © 2017 IEEE
Source estimation in noisy sparse component analysis
, Article 2007 15th International Conference onDigital Signal Processing, DSP 2007, Wales, 1 July 2007 through 4 July 2007 ; July , 2007 , Pages 219-222 ; 1424408822 (ISBN); 9781424408825 (ISBN) ; Babaiezadeh, M ; Jutten, C ; Sharif University of Technology
2007
Abstract
In this paper, a new algorithm for Sparse Component Analysis (SCA) in the noisy underdetermined case (i.e., with more sources than sensors) is presented. The solution obtained by the proposed algorithm is compared to the minimum l1 -norm solution achieved by Linear Programming (LP). Simulation results show that the proposed algorithm is approximately 10 dB better than the LP method with respect to the quality of the estimated sources. It is due to optimality of our solution (in the MAP sense) for source recovery in noisy underdetermined sparse component analysis in the case of spiky model for sparse sources and Gaussian noise. © 2007 IEEE
Unsupervised, fast and efficient colour-image copy protection
, Article IEE Proceedings: Communications ; Volume 152, Issue 5 , 2005 , Pages 605-616 ; 13502425 (ISSN) ; Kasaei, S ; Sharif University of Technology
2005
Abstract
The ubiquity of broadband digital communications and mass storage in modern society has stimulated the widespread acceptance of digital media. However, easy access to royalty-free digital media has also resulted in a reduced perception in society of the intellectual value of digital media and has promoted unauthorised duplication practices. To detect and discourage the unauthorised duplication of media, researchers have investigated watermarking methods to embed ownership data into media. However, some authorities have expressed doubt over the efficacy of watermarking methods to protect digital media. The paper introduces a novel method to discourage unauthorised duplication of digital...
Design and Implementation of Electrical Dust Control System Using DSP Processors
, M.Sc. Thesis Sharif University of Technology ; Vosoughi Vahdat, Bijan (Supervisor) ; Hashemi, Matin (Co-Advisor)An efficient synchronization circuit in multi-rate SDH networks
, Article Arabian Journal for Science and Engineering ; Volume 39, Issue 4 , April , 2014 , Pages 3101-3109 ; ISSN: 13198025 ; Hessabi, S ; Goudarzi, M ; Sharif University of Technology
Abstract
Single-rate synchronous digital hierarchy (SDH) networks contain one master block and several slave blocks and the slaves will synchronize themselves by the master clock frequency. However, the clock frequencies of master and slaves are different in multi-rate SDH networks and hence, the slaves require a synchronization circuit to match their clock frequencies with the master clock frequency. This research presents an efficient synchronization circuit for such networks. The proposed circuit occupies smaller area than the prior circuit and requires no clock alignment for its implementation. The circuit constraints are described and the maximum clock frequencies of master and slaves are...
Zero-power mismatch-independent Digital to Analog converter
, Article Conference Proceedings - 13th IEEE International NEW Circuits and Systems Conference, NEWCAS 2015, 7 June 2015 through 10 June 2015 ; June , 2015 , Page(s): - 4 ; 9781479988938 (ISBN) ; Sendi, M. S. E ; Nikoofard, A ; Sharifkhani, M ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2015
Abstract
A new switched-capacitor Digital to Analog converter (DAC) is presented. In this method, a ladder of series capacitors is used to generate the output voltage levels. A correction phase is used to increase the precision of the DAC. It is analytically shown that the proposed DAC is mismatch and process independent by virtue of the correction phase. That is after some correction phases, the effect of mismatch on the reference voltage levels on the ladder diminishes and an accurate voltage division is provided. It is proven that the whole process sinks no extra charge from the power supply
Multi-level asynchronous delta-sigma modulation based ADC
, Article ICIAS 2012 - 2012 4th International Conference on Intelligent and Advanced Systems: A Conference of World Engineering, Science and Technology Congress (ESTCON) - Conference Proceedings, 12 June 2012 through 14 June 2012 ; Volume 2 , June , 2012 , Pages 725-728 ; 9781457719677 (ISBN) ; Aghdam, E. N ; Najafi, V ; Sharif University of Technology
2012
Abstract
A Multi-level asynchronous delta sigma modulator consist of several Schmitt-triggers and a novel time-to-digital converter is presented as a core of a delta sigma modulation based analog to digital converter (ADC). The modulator firstly modulates the amplitude of its analog input signal to a multilevel asynchronous duty-cycle modulated signal. Then a time to digital converter (TDC) must be applied to generate digital representation of the received signal from the multi-level asynchronous duty-cycle modulated signal. A multi-level structure has been developed in this work while the prior works often used a single Schmitt. One of the most important limitations in conventional asynchronous...
A four bit low power 165MS/s flash-SAR ADC for sigma-delta ADC application
, Article IEEE International Conference on Electronics, Circuits, and Systems, 6 December 2015 through 9 December 2015 ; Volume 2016-March , 2016 , Pages 153-156 ; 9781509002467 (ISBN) ; Khorami, A ; Eslampanah Sendi, M. S ; Hajsadeghi, K ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
Abstract
A low power four bit mixed Successive Approximation Register (SAR)-Flash Analog to Digital Converter (ADC) for Sigma-Delta ADC applications is presented. The ADC uses three comparators in order to reduce the latency of typical SAR ADCs. Three comparators are used for conversion of 2 bits per one clock cycle. One of the Digital to Analog Converters (DACs) is replaced by three resistors which can save power and area. The ADC is simulated by Cadence Spectre using TSMC 0.18um COMS technology. The power consumption at 165MS/s and 1.8V supply voltage is 1.8mW. The SNDR and SFDR for 10MHz input are 19.8dB and 28.4dB, respectively
Microfluidics-Enabled multimaterial maskless stereolithographic bioprinting
, Article Advanced Materials ; Volume 30, Issue 27 , 2018 ; 09359648 (ISSN) ; Nieto, D ; Iglesias, L ; Goodarzi Hosseinabadi, H ; Maharjan, S ; Ruiz Esparza, G. U ; Khoshakhlagh, P ; Manbachi, A ; Dokmeci, M. R ; Chen, S ; Shin, S. R ; Zhang, Y. S ; Khademhosseini, A ; Sharif University of Technology
Wiley-VCH Verlag
2018
Abstract
A stereolithography-based bioprinting platform for multimaterial fabrication of heterogeneous hydrogel constructs is presented. Dynamic patterning by a digital micromirror device, synchronized by a moving stage and a microfluidic device containing four on/off pneumatic valves, is used to create 3D constructs. The novel microfluidic device is capable of fast switching between different (cell-loaded) hydrogel bioinks, to achieve layer-by-layer multimaterial bioprinting. Compared to conventional stereolithography-based bioprinters, the system provides the unique advantage of multimaterial fabrication capability at high spatial resolution. To demonstrate the multimaterial capacity of this...
A novel iterative Digital Down Converter
, Article 2007 IEEE International Conference on Telecommunications and Malaysia International Conference on Communications, ICT-MICC 2007, Penang, 14 May 2007 through 17 May 2007 ; February , 2007 , Pages 442-445 ; 1424410940 (ISBN); 9781424410941 (ISBN) ; Haghshenas, H ; Marvasti, F ; Sharif University of Technology
2007
Abstract
The digital radio receivers often have fast analog to digital converters delivering vast amount of data. However, in many cases, the signal of interest represents a small proportion of that bandwidth. A Digital Down Converter (DDC) is a filter that extracts the signal of interest from the incoming data stream. In this paper we first introduce an algorithm based on FFT which can be applied for simultaneous frequency shifting and decimating of Intermediate Frequency (IF) band signals, then a simplified iterative algorithm is suggested to improve the quality of reconstructed baseband signal. ©2007 IEEE
Design of Low Phase Noise DCO in All Digital Frequency Synthesizers
, M.Sc. Thesis Sharif University of Technology ; Atarodi, Mojtaba (Supervisor)
Abstract
A new class of design has been introduced in the RF circuits and Frequency Synthesizers, which is based on the digital circuits. Implementation of the digital synthesizers suppresses the need to use loop filter and thus reduces the loop lock time. In this thesis different topologies of digitally controlled oscillators using inductor and capacitor tank and all digital architectures used in high frequency all digital synthesizers in 0.18um CMOS technology has been inspected and simulated. Novel techniques introduced to improve the ring oscillator-based design’s specifications which doesn’t need inductor. Using the introduced techniques, the phase noise has been lessened acceptably with respect...
Circuit and Systematic Design of Low Power SAR ADC
, M.Sc. Thesis Sharif University of Technology ; Sharif Khani, Mohammad (Supervisor)
Abstract
Low power and high speed analog-to-digital converters (ADCs) are the key elements of communication and computing systems. There are several ADC structures such as delta-sigma, flash, pipeline, and successive approximation register (SAR) for different applications, albeit SAR ADCs are natural candidates of onchip designs for their low power and scalability benefits. Nowadays, SAR ADCs are widely being used in low-power moderate-resolution applications which need several tens of MS/s to low GS/s sampling rates. By virtue of the technology scaling power consumption of digital parts of a SAR ADC is reduced significantly. As a result, in a SAR ADC the power consumption of the digital-to-analog...