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A hardwired discrete simulation algorithm
, Article Scientia Iranica ; Volume 14, Issue 6 , 2007 , Pages 566-570 ; 10263098 (ISSN) ; Sharif University of Technology
Sharif University of Technology
2007
Abstract
The architecture of a hardwired simulator for implementation of a discrete event-driven simulation of digital systems at the logic level is presented. In the design of this system, attempts have been made to utilize techniques of high performance computing to have a system capable of simulating the digital circuits rapidly. The centralized event-driven simulation algorithm chosen here, has the advantages of being efficient and conceptually straightforward. The high reliability of the simulator has been taken care of through a collection of handshake signals between each two of the three main modules. © Sharif University of Technology, December 2007