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A low power pipeline A/D converter by using double sampling and averaging techniques
, Article 2006 IEEE Region 10 Conference, TENCON 2006, Hong Kong, 14 November 2006 through 17 November 2006 ; 2006 ; 21593442 (ISSN); 1424405491 (ISBN); 9781424405497 (ISBN) ; Atarodi, M ; Mehrmanesh, S ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2006
Abstract
A 1.8V, 10-Bit, 40-MS/s Pipeline analog-to-digital converter designed using 0.18-μmCMOS technology is presented. The new structure of the A/D converter is based on double sampling and averaging techniques. By the first technique, all the stage amplifiers are active at the both sampling and holding cycles. Averaging as the second technique minimizes the capacitance mismatch and exchanges the priority of input-referred noise and capacitance mismatch in the selection of the stage caps. The converter achieved a peak spurious-free- dynamic-range of 61 dB, maximum differential nonlinearity 0.5 of least significant bit (LSB), maximum integral linearity of 0.9 LSB, and power consumption of 5mW....
A high speed, high resolution, low voltage currentmode sample and hold
, Article IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005, Kobe, 23 May 2005 through 26 May 2005 ; 2005 , Pages 1417-1420 ; 02714310 (ISSN) ; Bakhtiar, M. S ; Sharif University of Technology
2005
Abstract
A low voltage current mode sample and hold (S/H) in 0.18μm technology with 1.5v supply voltage is presented. This S/H has 12-bit linearity, i.e., gain and nonlinearity errors of S/H are less than 0.02μA for 100uA input current. Maximum sampling rate for this structure is 100 MHz (using double sampling technique). © 2005 IEEE
A 1.5V 150MS/s current-mode sample-and-hold circuit
, Article 2005 European Conference on Circuit Theory and Design, Cork, 28 August 2005 through 2 September 2005 ; Volume 2 , 2005 , Pages 91-94 ; 0780390660 (ISBN); 9780780390669 (ISBN) ; Rajaee, O ; Jahanian, A ; Bakhtiar, M. S ; Sharif University of Technology
2005
Abstract
A high-speed current-mode sample-and-hold circuit is presented. This circuit allows for high sampling speed together with high linearity and precision. The sample-and-hold circuit has been designed and simulated in standard 0.18μm CMOS technology with 1.5V supply voltage. It is capable of operation with sampling frequency of 150MHz (300MHz using double sampling technique) for 12-bit accuracy using 3.7mW power
Continuous-time/discrete-time (CT/DT) cascaded sigma-delta modulator for high resolution and wideband applications
, Article WMED 2010 - 8th IEEE Workshop on Microelectronics and Electron Devices, 16 April 2010 through 16 April 2010 ; April , 2010 , Pages 33-36 ; 9781424465750 (ISBN) ; Sadeghi, K. H ; Ay, S. U ; Sharif University of Technology
2010
Abstract
This paper reports transistor-level design of a new continuous-time (CT), discrete-time (DT) cascaded sigma delta modulator (SDM). The combination of a CT first stage and a DT second stage was utilized to realize a high speed, high resolution analog-to-digital converter (ADC). Power consumption of CT first stage is lowered by optimizing the gain coefficients of CT integrators in a feedforward topology. Moreover double sampling (CDS) was used in second stage integrators to further reduce power consumption. Proposed new SDM is simulated in 0.18μm CMOS technology and achieves 84dB dynamic range for a 10MHz signal bandwidth. Total analog power dissipation measured was 44mW