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double-sampling-technique
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A high speed, high resolution, low voltage currentmode sample and hold
, Article IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005, Kobe, 23 May 2005 through 26 May 2005 ; 2005 , Pages 1417-1420 ; 02714310 (ISSN) ; Bakhtiar, M. S ; Sharif University of Technology
2005
Abstract
A low voltage current mode sample and hold (S/H) in 0.18μm technology with 1.5v supply voltage is presented. This S/H has 12-bit linearity, i.e., gain and nonlinearity errors of S/H are less than 0.02μA for 100uA input current. Maximum sampling rate for this structure is 100 MHz (using double sampling technique). © 2005 IEEE
A 1.5V 150MS/s current-mode sample-and-hold circuit
, Article 2005 European Conference on Circuit Theory and Design, Cork, 28 August 2005 through 2 September 2005 ; Volume 2 , 2005 , Pages 91-94 ; 0780390660 (ISBN); 9780780390669 (ISBN) ; Rajaee, O ; Jahanian, A ; Bakhtiar, M. S ; Sharif University of Technology
2005
Abstract
A high-speed current-mode sample-and-hold circuit is presented. This circuit allows for high sampling speed together with high linearity and precision. The sample-and-hold circuit has been designed and simulated in standard 0.18μm CMOS technology with 1.5V supply voltage. It is capable of operation with sampling frequency of 150MHz (300MHz using double sampling technique) for 12-bit accuracy using 3.7mW power