Sharif Digital Repository

Network throughput and energy conservation are two conflicting important performance metrics for wireless sensor networks. Since these two objectives are in conflict with each other, it is difficult to achieve them simultaneously. In this paper, a joint duty cycle scheduling and energy aware routing approach is proposed based on evolutionary game theory which is called DREG. Making a trade-off cand network throughput, the proposed approach prolongs the network lifetime. The paper is divided into the following sections: Initially, the discussion is presented on how the sensor nodes can be scheduled to sleep or wake up in order to reduce energy consumption in idle listening. The sensor... 

The main source of energy consumption in the current MAC protocols for wireless sensor networks is idle listening. To mitigate this problem, duty cycling is used. However, it increases data delivery latency. In this paper, we propose an Interference-aware duty-cycle MAC (IMAC) protocol for wireless sensor networks that uses cross-layer information to reserve multiple paths for each source and send data packets along them efficiently. IMAC also handles the existing interference between these paths such that data packets can be delivered in the minimum required number of cycles. Simulation results in ns-2 show that the proposed algorithm has an average reduction of 49% in data delivery latency... 

A multiplexing technique, which is based on duty-cycle division, is proposed. The channel multiplexing and demultiplexing are performed electrically at the single user bit rate, which is very economic. In a three-user system (3×10 Gb/s), the simulation results show that the best receiver sensitivity value achieved is -30.1 dBm with an optical signal-to-noise ratio (OSNR) of 22.3 dB, while the chromatic dispersion tolerance ranges from 192 to 280 ps/nm. Migration from 30 to 120 Gb/s is achieved with the penalty of 6.4 and 5.2 dB in the receiver sensitivity and OSNR, respectively, for the worst user  

In this paper, a new 1/4 rate clock linear phase detector (PD) structure for PLL-based clock and data recovery (CDR) circuits will be suggested. The proposed topology offers a more suitable PD for high speed applications compared to the conventional topologies. The effect of duty cycle variation on the operation of CDR has been also studied. Designed in a 0.18μm CMOS technology, the proposed PD consumes 16mA from a 1.8V voltage supply. © 2006 IEEE  

This article introduces a novel duty-cycle control circuit (DCC) preceding a delay-locked loop (DLL)-based clock frequency multiplier preventing the output duty-cycle over process, supply voltage and temperature (PVT) variations. However, the proposed DCC eliminates the effect of input duty-cycle variation and, hence, decreases the sensitivity to the input jitter and distortion. The circuit realisation in 0.5-μm CMOS technology shows that the duty-cycle variation at the output clock is less than 2.7%, while driving the digital section of a CODEC chip and also test pads. The analysis, confirmed by measurements, shows a stable and accurate response for the proposed clock generation unit (CGU).... 

In this era of digital communication systems, different factors are included in efficiency of a transceiver system. Binary PAM systems are one of these transceiver systems. Many aspects of such a system has been considered yet but this field needs more research on because this is the base of any communication system. In this paper, effects of transmitter and receiver filters, noise, duty-cycle and time mismatch between transmitter and receiver in a binary baseband PAM transceiver system is analyzed. Simulation is performed to analyze the above effects on a typical communication system with 10 bits of transmit. MATLAB software is being employed for simulations  

The effect of clock skew and duty-cycle on the performance of high-Q N-phase band-pass filters (BPFs) have been examined in this paper. Following a mathematical approach and using the analytical derivations carried out, the effects of such non-idealities as clock skew and duty-cycle error are determined in an N-path filter. It is analytically proved that image signals from all integer multiples of the clock signal, rather than just those at (1 ± kN) multiples of the clock signal, land atop the wanted RF spectrum. In a real world clock generator, with non-idealities in effect, filtering property and proper behavior of the filter is adversely affected. Finally, system level simulation along... 

This paper describes the effects of using direct and pulse current on composition and corrosion resistance of Fe-Ni-Cr alloy coatings. In both direct and pulse current electrodeposition, increasing the current density has a decreasing effect on Fe and Ni and an increasing influence on Cr. In pulse current electrodeposition, duty cycle has a greater effect than frequency on composition of the alloy coating, particularly in the range of 10-50%. In this range, by increasing the duty cycle, Ni decreases, Fe sharply increase and Cr shows an increasing trend. Following a study of the microhardness of coatings, it is determined that the microhardness increases about 1.5 times by pulse current... 

The application of time-interleaved structure leads to new amplitude and time errors while reducing many static and dynamic errors. In this case, both amplitude and time error are decreased by circuit structures integrated into a 7-bit DAC. In the present study, a new structure was proposed based on the randomization of two-interleaved paths in order to reduce the amplitude error, which can be extended to the N-channels-interleaved. In order to reduce the cycle-duty-error, a self-correction structure based on calculating the amplitude of the error before and measuring the time of this error along with the passage of the main signal through the output multiplexer is provided. The advantage of... 

Since ultraviolet (UV) irradiation cannot be applied for a long time in practical applications, it is necessary to develop a narrow band gap photocatalyst to decompose environmental pollutants under visible irradiation. In this research, (WO3)x-(TiO2)1-x nano-porous layers were fabricated by micro arc oxidation (MAO) and influence of the electrical current type on their physical and chemical properties was investigated. Morphological studies, performed by SEM technique, revealed that pore size and roughness decreased with the frequency and increased with the duty cycle. The pulse-grown layers had a finer structure when compared to those fabricated under direct current. XRD and XPS results... 

TiO2 layers were grown via pulse type microarc oxidation process under different applied voltages, frequencies, and duty cycles. Surface chemical composition and phase structure of the synthesized layers were studied utilizing X-ray photoelectron spectroscopy (XPS) and X-ray diffraction (XRD). Furthermore, scanning electron microscope (SEM) and atomic force microscope (AFM) were employed to investigate surface morphology and topography of the layers. It was revealed that the layers had a porous structure with both anatase and rutile phases. The anatase relative content in the layers increased with the applied frequency; meanwhile, it decreased with duty cycle at low applied voltages, but... 

A Multi-level asynchronous delta sigma modulator consist of several Schmitt-triggers and a novel time-to-digital converter is presented as a core of a delta sigma modulation based analog to digital converter (ADC). The modulator firstly modulates the amplitude of its analog input signal to a multilevel asynchronous duty-cycle modulated signal. Then a time to digital converter (TDC) must be applied to generate digital representation of the received signal from the multi-level asynchronous duty-cycle modulated signal. A multi-level structure has been developed in this work while the prior works often used a single Schmitt. One of the most important limitations in conventional asynchronous... 

In this paper, a reliable low power single phase grid-connected inverter for photovoltaic modules is proposed. The inverter has improved lifetime since large electrolytic capacitor is replaced with small film capacitor due to circuit topology, power processing and proper control scheme. Thus the main limiting component in single phase grid connected inverters is obviated. The proposed inverter consists of two power processing stages. First a dual active bridge (DAB) converter boosts the voltage of PV panel to approximately 440 V and eliminates impact of high dc bus voltage ripples. A proper feed forward control is proposed to regulate the dc bus voltage with high ripple. Simulation results... 

The aim of this paper is to study the influence of frequency in pulse electrodeposition, on the current efficiency, Ni content and surface morphology of deposits from a novel cyanide-citrate electrolyte with 20 mM gold as KAu(CN) 2 and 7 mM NiSO 4, with the aim of design of experiment by respond surface method (RSM). Frequency was in the range of 1-200 Hz in constant average current density, temperature, and duty cycle of 7 mA/cm 2, 59 °C and 55% respectively. Composition of the deposits was determined by atomic absorption spectroscopy (AAS). Additionally, deposits were characterized by scanning electron microscopy (SEM), and Energy-dispersive X-ray spectroscopy (EDS). It was shown that from... 

V2O5-TiO2 nanostructured porous layers were grown through micro arc oxidation of titanium in vanadate containing electrolytes. This study sheds light on the effect of the electric current type on the photocatalytic performance of the layers. Surface morphology of the layers was investigated by SEM. The results revealed a porous structure with a pores size of 30-180 nm depending on the frequency and the duty cycle. A uniform porous structure was obtained under the pulse-DC regime. Topographical investigations revealed a rough surface which is favorable for catalytic applications. Our XRD and XPS results showed that the layers consisted of anatase, rutile, and vanadium oxide phases whose... 

Negative Bias Temperature Instability (NBTI) in CMOS devices is known as the major source of aging effect which is leading to performance and reliability degradation in modern processors. Instruction-cache (I-cache), which has a decisive role in performance and reliability of the processor, is one of the most prone modules to NBTI. Variations in duty cycle and long-time residency of data blocks in I-cache lines (stress condition) are the two major causes of NBTI acceleration. This paper proposes a novel I-cache management technique to minimize the aging effect in the I-cache SRAM cells. The proposed technique consists of a smart controller that monitors the cache lines behavior and... 

The Cúk converter operating in discontinuous capacitor voltage mode (DCVM) inherently benefits from PFC features as unity power factor can be achieved by using a constant duty cycle and switching frequency. In this paper, the switch network modeling technique is applied to the Cúk converter operating in DCVM in order to develop its small-signal model under the assumption that it is fed by a dc voltage source. Afterwards, the model is extended to derive the small-signal behavior of the converter while operating as a PFC converter. The validity of the proposed model is confirmed by both simulation and experimental results  

Composite coatings containing self-lubricant particles like graphite, MoS2, PTFE are extensively used to decrease the coefficient of friction of tribo-surfaces. The aim of this study is to investigate the effect of pulse electrodeposition parameters on particle codeposition process and characteristics of bronze-graphite composite coatings electrodeposited from cyanide-stannate bronze electroplating bath. Results showed a slight increase in tin content and a promising increase in hardness of bronze coating by a decrease in duty cycle at constant average current density. Both tin content of the coating and grain refinement seem to participate in hardness enhancement. By increasing the... 

Cúk Converter operating in discontinuous capacitor voltage mode is an inherent PFC converter in which, unity power factor can be achieved using constant duty cycle and switching frequency. In this paper, a reduced-order switch network modeling technique is applied to Cúk converter operating in DCVM in order to derive small-signal model of the converter assuming a dc voltage source as the input source of the converter. This model is extended to derive the small-signal behavior of the converter while operating as a PFC converter. The validity of the proposed model is confirmed by both simulation and experimental results. Afterwards, a new control strategy is proposed in which switching...