Sharif Digital Repository

This paper presents a low power SAR ADC utilizing pipelining to increase the resolution up to 12 bits while maintaining a high speed sampling rate. Novel system level modifications and also new comparator architecture are proposed to optimize the power consumption. The ADC is designed and simulated in 0.18um CMOS technology by 1.2v supply voltage consuming 4.5mW power at 40MS/s sampling rate. The results indicates an effective number of bits (ENOB) of 11.04 bit and a challenging FOM of 54.9 fj/conversion which verifies the competence of proposed method  

A low power 4-bit flash ADC is proposed. A new power reduction technique is employed which deactivates the unused blocks in the converter structure in order to reduce the power consumption. A new method for built-in threshold voltage generation together with a new offset calibration method is used to further reduce the power consumption in the converter. Monte-Carlo simulation shows that after calibration both the INL and the DNL are lower than 0.35 LSB. The converter achieves 3.5 effective number of bits (ENOB) at 1.2 GS/s sampling rate after the offset calibration is performed. It consumes 10 mW from a 1.8 V supply, yielding a FoM of 560 fJ/conversion.step in a 0.18 μm standard CMOS... 

A low power 4-bit, 1.6 GS/s flash ADC is presented. A new power reduction technique which masks the unused blocks in a semi-pipeline chain of latches and encoders is introduced. The proposed circuit determines the unused blocks based on a pre-sensing of the signal. Moreover, a reference voltage generator with very low static power dissipation is used. Novel techniques to reduce the sensitivity to dynamic noise are proposed to suppress the noise effects on the reference generator. The proposed circuit reduces the power consumption by 20 percent compared to the conventional structure when a Nyquist rate OFDM signal is applied. The INL and DNL of the converter are smaller than 0.3 LSB after... 

A low power 10 bit, 40 MS/s pipeline analog to digital converter is presented. A number of low-power techniques are proposed in various levels of abstraction. In circuit level, a low power class A/AB opamp with direct common-mode-feedback circuit (CMFB) is proposed which significantly reduces power in the opamps. In backend design, optimal series capacitors are layed out to break the deadlock between the mismatch and loading effect of the first stage capacitors. A customized software tool is developed based on the proposed opamp and architecture which provides optimum stage scaling factors, tail current and opamp transistor sizes. Simulations in 0.13um CMOS technology show that the ADC...