Sharif Digital Repository

A new family of sampled-data filters in which accuracy is a function of the ratio of the resistors is introduced. It is shown that this structure is suitable for low-voltage high-speed applications. A biquad filter with a quality factor of 10 and a clock frequency of 60MHz consuming only 2mW power is also presented  

This article presents a very low-power clock and data recovery (CDR) circuit with 8 parallel channels achieving an aggregate data rate of 20 Gbps. A structural top-down design methodology has been applied to minimize the power dissipation while satisfying the required specifications for short-haul receivers. Implemented in a 0.18μm digital CMOS technology, total power dissipation is 70.2mW or 3.51mW/Gbps/Ch and each channel occupies 0.045 μm2 silicon area. © 2005 IEEE  

In this paper, the effect of imperfections on the behavior of N-path filters is investigated. Exact mathematical derivations are presented which describe the effect of clock skew and finite fall/rise time on the impedance transformation behavior of N-path filters. In the ideal case, the N-path filter is supposed to provide a short-circuit to the ground for undesired frequency contents and an open-circuit for the desired signal so that it lies within the passband of the filter. It is shown that clock skew and finite clock fall/rise time result in a non-zero impedance for frequency contents other than the clock frequency and a smaller impedance for the desired voltage. In a real circuit with... 

The effect of clock skew and duty-cycle on the performance of high-Q N-phase band-pass filters (BPFs) have been examined in this paper. Following a mathematical approach and using the analytical derivations carried out, the effects of such non-idealities as clock skew and duty-cycle error are determined in an N-path filter. It is analytically proved that image signals from all integer multiples of the clock signal, rather than just those at (1 ± kN) multiples of the clock signal, land atop the wanted RF spectrum. In a real world clock generator, with non-idealities in effect, filtering property and proper behavior of the filter is adversely affected. Finally, system level simulation along... 

This paper presents a quadrature-clock generator based on a novel low-power ring oscillator with a wide frequency tuning range and low temperature variations. The proposed ring oscillator consists of two differential delay cells with a new controllable capacitive load of an MOS transistor. The wide tuning range is achieved due to transistor utilization in different regions and considering its resistance not to narrow down the frequency range. Delay cells are biased with a minimum possible value of a proportion to absolute temperature current to decrease frequency variations to temperature while the power consumption is kept low. The validation of the proposed methods is proved by circuit... 

In this paper, a new all optical phase-locked loop (OPLL) is proposed and analyzed. The scheme relies on using two optical Kerr shutters to reveal the OPLL's error signal. The set of optical Kerr shutters and the subsequent low-speed photodetectors realize two nonlinear cross-correlations between the local clock pulse stream (called pump in Kerr shutter notations) and the time-shifted replicas of the incoming received data signal (called probe). The outputs of the cross-correlators are subtracted to form the error signal of the OPLL. We characterize the mathematical structure of the proposed OPLL and identify its two intrinsic sources of phase noise, namely, randomness of the received... 

In many synchronous digital systems especially those used in mobile applications, the system is exposed to sever shaking that may lead to a failure in the clock generator. In this paper we present an effective method to tolerate the faults on the clock signal that are due to defects in external oscillators. Our technique utilizes no Phase-Lock Loops (PLL), no Delay-Locked Loops (DLL) and no high frequency oscillators because of their drawbacks so that it needs neither more effort to meet Electro-Magnetic Compatibility (EMC) and requirements nor extra hardware to implement DLLs. We have formally evaluated the meta-stability of our technique. This evaluation shows that our technique reliably... 

In this paper, we analyze and discuss the performance limits of optical clock recovery systems using a phase-locked loop (PLL) structure with nonlinear two-photon absorption (TPA) phase detection scheme. The motivation in analyzing the aforementioned optical PLL with TPA receiver structure is due to a recent successful experiment reported in [8]. We characterize the mathematical structure of PLLs with TPA, so as to evaluate the performance limits on optical clock recovery mechanism. More specifically, we identify two intrinsic sources of phase noise in the system namely, the ON-OFF nature of the incoming data pulses and the detector's shot noise that ultimately limit the performance of the...