Sharif Digital Repository

Absolutely maximally entangled (AME) states are pure multi-partite generalizations of the bipartite maximally entangled states with the property that all reduced states of at most half the system size are in the maximally mixed state. AME states are of interest for multipartite teleportation and quantum secret sharing and have recently found new applications in the context of high-energy physics in toy models realizing the AdS/CFT-correspondence. We work out in detail the connection between AME states of minimal support and classical maximum distance separable (MDS) error correcting codes and, in particular, provide explicit closed form expressions for AME states of n parties with local... 

Spin-Transfer Torque RAM (STT-RAM) is a promising alternative to SRAM for implementing on-chip L2 and L3 caches. One of the most critical challenges in STT-RAM is reliability due to limited write endurance, which results in insufficient lifetime, as well as various types of errors. Previous studies have focused on either presenting various cache architectures/management techniques to improve the lifetime of STT-RAM caches or utilizing different Error Correcting Codes (ECCs) to protect against the permanent and transient errors. However, there is no quantitative analysis in the literature to determine the impact of ECCs on the lifetime of the STT-RAM caches. This paper formulates this impact... 

Due to serious problems of SRAM-based caches in nano-scale technologies, researchers seek for new alternatives. Among the existing options, STT-RAMseems to be themost promising alternative.With high density and negligible leakage power, STT-RAMs open a new door to respond to future demands of multi-core systems, i.e., large on-chip caches. However, several problems in STT-RAMs should be overcome to make it applicable in on-chip caches.High probability of write error due to stochastic switching is amajor problemin STT-RAMs. Conventional Error-CorrectingCodes (ECCs) impose significant area and energy consumption overheads to protect STT-RAMcaches. These overheads in multi-core processors with... 

Spin-Transfer Torque Magnetic RAM (STT-MRAM) as one of the most promising replacements for SRAMs in on-chip cache memories benefits from higher density and scalability, near-zero leakage power, and non-volatility, but its reliability is threatened by high read disturbance error rate. Error-Correcting Codes (ECCs) are conventionally suggested to overcome the read disturbance errors in STT-MRAM caches. By employing aggressive ECCs and checking out a cache block on every read access, a high level of cache reliability is achieved. However, to minimize the cache access time in modern processors, all blocks in the target cache set are simultaneously read in parallel for tags comparison operation... 

The wear-out of flash-based Solid-State Drives (SSDs) is a main concern that significantly affects their reliability. One major parameter that accelerates SSD wear-out is the number of write-cycles committed to flash chips. The number of write-cycles in SSD-based disk subsystem is highly dependent on the erasure code implemented in Redundant Array of Independent Disks (RAIDs). In this paper, we investigate the impact of erasure codes and the configuration of storage subsystems (i.e., the number of disks participated in the RAID array and stripe unit size) on the endurance of storage systems. The number of write-cycles is considered as a metric to evaluate the endurance of storage system. We... 

Data integrity of words coming out of the caches needs to be checked to assure their correctness. This paper proposes a cache placement scheme, which provides high performance as well as high fault detection coverage. In this scheme, the cache space is divided into sets of different sizes. Here, the length of tag fields associated to each set is unique and is different from the other sets. The other remained bits of tags are used for protecting the tag using a fault detection scheme e.g., generalized parity. This leads to protect the cache without compromising performance and area with respect to the similar one, fully associative cache. The results obtained from simulating some standard... 

In this paper, the multiuser performance of a multicarrier frequency-hopping (MC-FH)CDMA system employing non-coherent detection is evaluated. We derive the bit error rate of the system for both uncoded and coded systems in AWGN and slowly frequency-selective Rayleigh fading channel, based on Gaussian distribution assumption for the decision variable. We use a practical low-rate convolutional error correcting code, which does not require any extra bandwidth further than what is needed by the uncoded scheme. Our numerical results indicate that the coded scheme significantly outperforms the uncoded scheme in both AWGN and fading channels. Furthermore, it is observed that the performance... 

In this paper, we provide multiuser performance analysis of a multicarrier frequency-hopping (MC-FH) code-division multiple-access system as first introduced in the work of Lance and Kaleh. We propose to use a practical low-rate convolutional error-correcting code in this system, which does not require any additional bandwidth than what is needed by the frequency-hopping spread-spectrum modulation. We provide multiuser exact performance analysis of the system for both uncoded and coded schemes in additive white Gaussian noise and fading channels for a single-user correlator receiver. We also derive the performance analysis of the system based on a Gaussian distribution assumption for... 

In this paper, we consider using practical low-rate error correcting codes in fiber-optic code division multiple-access (CDMA) communication systems. To this end, a different method of low-rate channel coding is proposed. As opposed to the conventional coding schemes, this method does not require any further bandwidth expansion for error correction in fiber-optic CDMA communication systems. The low-rate channel codes that are used for demonstrating the capabilities of the proposed method are super-orthogonal codes. These codes are near optimal and have a relatively low complexity. We evaluate the upper bounds on the bit-error probability of the proposed coded fiber-optic CDMA system assuming... 

Spin-Transfer Torque Random Access Memories (STT-RAMs) are a promising alternative to SRAMs in on-chip caches. STT-RAMs face with a high error rate in write operations due to stochastic switching. To alleviate this problem, Error-Correcting Codes (ECCs) are commonly used, which results in a significant area and energy consumption overhead. This paper proposes an efficient technique, so-called Adaptive Way Allocation for Reconfigurable ECCs (AWARE), to correct write errors in STT-RAM caches. AWARE exploits the asymmetric error rate in cell switching directions, which leads to data-dependent write error rates, to reduce the ECC overheads without compromising the reliability of the cache. To... 

Spin-Transfer Torque Random Access Memories (STT-RAMs) are a promising alternative to SRAMs in on-chip caches. STT-RAMs face with a high error rate in write operations due to stochastic switching. To alleviate this problem, Error-Correcting Codes (ECCs) are commonly used, which results in a significant area and energy consumption overhead. This paper proposes an efficient technique, so-called Adaptive Way Allocation for Reconfigurable ECCs (AWARE), to correct write errors in STT-RAM caches. AWARE exploits the asymmetric error rate in cell switching directions, which leads to data-dependent write error rates, to reduce the ECC overheads without compromising the reliability of the cache. To... 

Polar codes are novel and efficient error-correcting codes with low encoding and decoding complexities. These codes have a channel-dependent generator matrix, which is determined by the code dimension, code length and transmission channel parameters. A variant of the McEliece public-key cryptosystem based on polar codes, called the PKC-PC, is studied. Since the structure of the polar codes' generator matrix depends on the parameters of the channel, the authors have used an efficient approach to conceal their generator matrix. The proposed approach is based on a random selection of rows of the matrix by which a random generator matrix is constructed. Using the characteristics of polar codes... 

An extended version of Lagrange interpolation is developed for coding of images in real field in a way that at the receiver, one can restore the lost portions of the images. The proposed solution is similar to channel coding techniques, but it is done before source coding at the transmitter and after decoding of the compressed data at the receiver. Our proposed solution is faster than the other one reported in the literature when the size of damaged blocks is large  

Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) is a promising alternative to SRAM in cache memories. However, STT-MRAMs face with high probability of write errors due to its stochastic switching behavior. To correct the write errors, Error-Correcting Codes (ECCs) used in SRAM caches are conventionally employed. A cache line consists of several codewords and the data bits are selected in such a way that the maximum correction capability is provided based on the error patterns in SRAMs. However, the different write error patterns in STT-MRAM caches leads to inefficiency of conventional ECC configurations. In this paper, first we investigate the efficiency of ECC configurations... 

Spin-Transfer Torque Magnetic RAM (STT-MRAM) is a promising alternative for SRAMs in on-chip cache memories. Besides all its advantages, high error rate in STT-MRAM is a major limiting factor for on-chip cache memories. In this paper, we first present a comprehensive analysis that reveals that the conventional Error-Correcting Codes (ECCs) lose their efficiency due to data-dependent error patterns, and then propose an efficient ECC configuration, so-called ROBIN, to improve the correction capability. The evaluations show that the inefficiency of conventional ECC increases the cache error rate by an average of 151.7% while ROBIN reduces this value by more than 28.6x. © 2019 Association for... 

Hybrid Multi-Level Cache Architectures (HCAs) are promising solutions for the growing need of high-performance and cost-efficient data storage systems. HCAs employ a high endurable memory as the first-level cache and a Solid-State Drive (SSD) as the second-level cache. Spin-Transfer Torque Magnetic RAM (STT-MRAM) is one of the most promising candidates for the first-level cache of HCAs because of its high endurance and DRAM-comparable performance along with non-volatility. However, STT-MRAM faces with three major reliability challenges named Read Disturbance, Write Failure, and Retention Failure. To provide a reliable HCA, the reliability challenges of STT-MRAM should be carefully addressed....