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error-detection-and-recovery
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Low-cost scan-chain-based technique to recover multiple errors in TMR systems
, Article IEEE Transactions on Very Large Scale Integration (VLSI) Systems ; Volume 21, Issue 8 , 2013 , Pages 1454-1468 ; 10638210 (ISSN) ; Miremadi, S. G ; Asadi, H ; Fazeli, M ; Sharif University of Technology
2013
Abstract
In this paper, we present a scan-chain-based multiple error recovery technique for triple modular redundancy (TMR) systems (SMERTMR). The proposed technique reuses scan-chain flip-flops fabricated for testability purposes to detect and correct faulty modules in the presence of single or multiple transient faults. In the proposed technique, the manifested errors are detected at the modules' outputs, while the latent faults are detected by comparing the internal states of the TMR modules. Upon detection of any mismatch, the faulty modules are located and the state of a fault-free module is copied into the faulty modules. In case of detecting a permanent fault, the system is degraded to a...
ScTMR: A scan chain-based error recovery technique for TMR systems in safety-critical applications
, Article Proceedings -Design, Automation and Test in Europe, DATE, 14 March 2011 through 18 March 2011 ; March , 2011 , Pages 289-292 ; 15301591 (ISSN) ; 9783981080179 (ISBN) ; Miremadi, S. G ; Asadi, H ; Sharif University of Technology
2011
Abstract
We propose a roll-forward error recovery technique based on multiple scan chains for TMR systems, called Scan chained TMR (ScTMR). ScTMR reuses the scan chain flip-flops employed for testability purposes to restore the correct state of a TMR system in the presence of transient or permanent errors. In the proposed ScTMR technique, we present a voter circuitry to locate the faulty module and a controller circuitry to restore the system to the fault-free state. As a case study, we have implemented the proposed ScTMR technique on an embedded processor, suited for safety-critical applications. Exhaustive fault injection experiments reveal that the proposed architecture has the error detection and...
Software-based control flow error detection and correction using branch triplication
, Article Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011, 13 July 2011 through 15 July 2011 ; July , 2011 , Pages 214-217 ; 9781457710551 (ISBN) ; Fazeli, M ; Rad, H. I ; Miremadi, S. G ; Sharif University of Technology
2011
Abstract
Ever Increasing use of commercial off-the-shelf (COTS) processors to reduce cost and time to market in embedded systems has brought significant challenges in error detection and recovery methods employing in such systems. This paper presents a software based control flow error detection and correction technique, so called branch TMR (BTMR), suitable for use in COTS-based embedded systems. In BTMR method, each branch instruction is triplicated and a software interrupt routine is invoked to check the correctness of the branch instruction. During the execution of a program, when a branch instruction is executed, it is compared with the second redundant branch in the interrupt routine. If a...