Sharif Digital Repository

In software programs, most of the time, there is a chance of error, even though they are tested carefully. Finding error-related pieces of code is one of the most complicated tasks and it can make incorrect results if done manually. Semi-automated and fully-automated methods have been introduced to overcome this issue. The rapid growth of developing Smart Mobile Applications (SMAs) in recent years, competition among the development teams and many other factors have increased the chance of errors, and hence, the quality of these applications have reduced. There are two approaches to test SMAs in order to reach a high degree of quality: (i) using existing traditional methods and adapting them... 

Changes in the physicochemical conditions of process unit, even under control, may lead to what are generically referred to as faults. The cognition of causes is very important, because the system can be diagnosed and fault tolerated. In this article, we discuss and propose an artificial neural network that can detect the incipient and gradual faults either individually or mutually. The main feature of the proposed network is including the fault patterns in the input space. The scheme is examined through a sample unit with five probable occurring faults. The simulation results indicate that the proposed algorithm can detect both single and two simultaneous faults properly  

In this paper a new post fault operation strategy is proposed for modular multilevel converter (MMC). The conventional MMC fault tolerant operation methods use redundant cells in spinning or cold reserve schemes, however in this work the MMC fault tolerant operation is achieved without requiring any redundant cells. The introduced strategy modifies capacitors reference voltages and arms modulation reference waveforms in faulty leg of MMC while other legs operate normally. The applied technique leads to having some degree of overvoltage in faulty leg capacitors which could be neglected since the number of cells is high. Simple realization and significant economic savings would be attained as... 

The switch level is an abstraction level between the gate level and the electrical level, offers many advantages. Switch level simulators can reliably model many important phenomena in CMOS circuits, such as bi-directional signal propagation, charge sharing and variations in driving strength. However, the fault simulation of switch level models is more time-consuming than gate level models. This paper presents a method for fast fault emulation of switch level circuits using FPGA chips. In this method, gates model switch level circuits and we can emulate mixed gate-switch level models. By the use of this method, FPGA chips can be used to accelerate the fault injection campaigns into switch... 

As the semiconductor industry advances to the deep sub-micron and nano technology points, the on-chip components are more prone to the defects during manufacturing and faults during system operation. Consequently, fault tolerant techniques are essential to improve the yield of modern complex chips. We propose a fault-tolerant routing algorithm that keeps the negative effect of faulty components on the NoC power and performance as low as possible. Targeting intermittent faults, we achieve fault tolerance by employing a simple and fast mechanism composed of two processes: NoC monitoring and route adaption. Experimental results show the effectiveness of the proposed technique, in that it offers... 

In this paper, we have proposed a fast and easy-to-develop FPGA-based fault injection technique. This technique uses the Altera FPGAs debugging facilities in order to inject SEU fault model in both flip-flops and memory units. Since this method uses the FPGAs built-in facilities, it imposes a negligible performance and area overhead on the system. The experimental results on Leon2 processor shows that the proposed technique is on average four orders of magnitude faster than a simulation-based fault injection  

Fault injection methods have been used for analyzing dependability characteristics of systems for years. In this paper we propose a practical mixed-signal fault injection flow that is fast as well as accurate. We described three classes of most common faults: i) Single event transients, ii) Electro-Magnetic interference and iii) Power disturbance faults. Fault models are implemented directly into circuit's devices using behavioral fault description in Verilog-A language. As an example for dependability evaluation, some test circuits have been prepared and the results of fault injection on their designs have been reported  

Over the last two decades there have been numerous reports from different seismically active regions of the world that thermal infrared (TIR) anomalies can be identified around the epicentral areas before major earthquakes [e.g. (Tronin et al., 2002)]. The TIR anomalies reportedly appear as early as 14 to 7 days before the seismic events and affect areas as large as 1000s to 100,000s km2 in size. Our case study for detection of TIRs using NOAA-AVHRR data(Band 4) is an Ms = 5.1 earthquake that occurred on 14th October 2004 near Ravar in Kerman province located in Loot and Tabas deserts, southeast-central Iran. The area is part of the Golbaf-Sirj seismogenic zone. It includes major faults... 

Cooling water is used to remove the heat from stator bar of large turbogenerators and prevent additional temperature rise. Blockage of these channels leads to heat traps along the stator bar and its temperature failure. In addition, transposition of strands in a bar causes accumulation of heat in some parts of stator bar because of non-uniform arrangement of cooling channels especially when some of channels are blocked. In this paper, effect of cooling water channels blockage is studied using a precise thermal model. It is shown that such heat traps cause additional temperature rise in stator bars and this phenomenon can not be detected by thermal sensors of turbogenerator. Laboratory and... 

This paper presents a unified passive–active fault-tolerant control strategy to compensate the loss of actuators’ effectiveness. The proposed approach is capable of handling the system in pre- and post-fault diagnosis intervals by passive and active approaches, respectively. The stability of the designed system is independent of the accuracy of information provided by the fault detection and diagnosis unit, however, a precise estimation could improve the conservation. Actuator saturation and L∞ disturbances effects are considered in the design stage. The trade-off between maximising the domain of attraction and minimising the effects of L∞ disturbances is tackled by developing a non-constant... 

This paper presents a unified passive–active fault-tolerant control strategy to compensate the loss of actuators’ effectiveness. The proposed approach is capable of handling the system in pre- and post-fault diagnosis intervals by passive and active approaches, respectively. The stability of the designed system is independent of the accuracy of information provided by the fault detection and diagnosis unit, however, a precise estimation could improve the conservation. Actuator saturation and L ∞ disturbances effects are considered in the design stage. The trade-off between maximising the domain of attraction and minimising the effects of L ∞ disturbances is tackled by developing a... 

Low power consumption and high-reliability are often major objectives in the design of embedded systems. To reduce power consumption, embedded systems usually employ system-level power management techniques, e.g. Dynamic Voltage Scaling (DVS) and Dynamic Power Management (DPM). To achieve high reliability, embedded systems often exploit fault-tolerant techniques. Fault-tolerant techniques are in a trade-off with energy consumption, peak-power consumption, and temperature. Thus, different methods have been introduced that simultaneously consider reliability and power consumption as the system constraints. Several novel methods have been proposed in previous works to reduce the power... 

This paper gives the final Solution for vibration reduction in a centrifugal pump. Vibration measurement in different conditions has been carried out in order to find the main reason for excessive vibration of the pumps. In the first stage several parameters including cavitation, not working in the pump design condition and mechanical and electrical faults assumed to be the reason for the pump vibration. By vibration analysis it is found that the major reason for the pump vibration is working in off design conditions. More over dissolved air in the suction fluid can possibly cause two-phase flow leading to the pump vibration. For solving both problems considering pump performance curves it... 

Process Fault Diagnosis (PFD) involves interpreting the current status of the plant given sensor readings and process knowledge. There has been considerable work done in this area with a variety of approaches being proposed for PFD. Neural networks have been used to solve PFD problems in chemical processes, as they are well suited for recognizing multi-dimensional nonlinear patterns. In this work, the use of Hierarchical Artificial Neural Networks (HANN) in diagnosing the multi-faults of a chemical process are discussed and compared with that of Single Artificial Neural Networks (SANN). The lower efficiency of HANN, in comparison to SANN, in PFD is elaborated and analyzed. Also, the concept... 

In this paper we present a new fault model for testing bus components using their functionality. With the aim of a new fault model definition all components in a bus except cores of the SoC will be tested as fast as possible. According to the proposed method in this paper, at first, wires and small components will be tested by marching test patterns as the test data and, after that based on a proposed method; the new format faults for the bus will be used. Using AMBA-AHB as the experimental result, the new fault model shows efficiency in comparison with corresponding stuck-at  

In order to prevent further damage and to provide the continuity of service of six-leg converter in case of open-switch fault, it is mandatory to perform fast fault detection and converter reconfiguration schemes. Extra sensors are needed to detect the faults rapidly. In this paper, a very fast FPGA-based fault detection scheme is presented that minimizes the number of additional voltage sensors. A six-leg fault tolerant converter topology without redundancy and with bidirectional power flow is studied. First simulations are carried out to evaluate the proposed fault detection principle and the fault tolerant converter topology. The fully digital control and the fault detection are... 

This paper proposes a new fault detection method for the modular multilevel converter (MMC) semiconductor power switches. While in common MMCs, the modules capacitor voltages are measured directly for control purposes, in this paper voltage measurement point changes to module output terminal improving fault diagnosis ability. Based on this measurement reconfiguration, a novel fault detection algorithm is designed for MMCs semiconductor power switches. The open circuit and short circuit faultsare detected based on unconformity between modules output voltage and switching signals. Simulations results confirm accurate and fast operation of the proposed algorithm in faulty module diagnosis.... 

Automation systems provide substantial improvement in service reliability through speeding up fault management procedure. However, this is at expense of high investments whose justification needs thorough cost/worth analyses. This paper introduces a mathematical model to optimally place automation system devices within distribution networks. The model establishes a trade-off between service reliability improvements and the relevant costs. Among different automation system devices, fault indicators and remote controlled switches are considered here. Also, the impact of manual switches is regarded since their number and location significantly affect the solution of the placement problem. The... 

Due to several advantages, three-phase Dual Active Bridge (DAB) converter is widely used in numerous applications nowadays. On the other hand, this converter is very vulnerable to Transistor Open-Circuit Fault (TOCF). Therefore, a fault-tolerant (FT) scheme has been proposed in this paper to solve the problem. First, normal and faulty conditions are investigated, and according to the results, a fault-diagnosis (FD) approach is introduced. Using the outcomes of FD unit, a new post-fault strategy is proposed for the converter. The FD method is based on the DC component of transformer phase currents, and the basis of FT technique is shedding the faulty phase. Some benefits of the proposed... 

This paper presents an analysis of the effects and propagation of faults in the open-core 32-bit OpenRISC 1200 microprocessor. The analysis is based on a total of 13,000 transient faults injected into 65 parts of the CPU module in the OpenRISC 1200 core described at the RTL model. A comparison of the effects of faults on the various parts of the CPU including the pipeline's registers, the CPU component such as the register file, the control unit, and the ALU, and the data and address buses is done. It is shown that about 30%, 40% and 27% of injected faults terminated in address, data, and control errors respectively. About 28% of all injected faults resulted in failures. © 2008 IEEE