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    A non-intrusive portable fault injection framework to assess reliability of FPGA-based designs

    , Article FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology ; 2013 , Pages 398-401 ; 9781479921990 (ISBN) Ghazaani, E. A ; Ghaderi, Z ; Miremadi, S. G ; Sharif University of Technology
    2013
    Abstract
    This paper proposes a full-featured fault injection framework to assess reliability of FPGA-based designs. The framework provides non-intrusiveness, portability, flexibility and performance in reliability evaluation of FPGA-based designs against adverse effects of SEUs. It works in a non-intrusive manner, allowing the reliability of ready-to-be-released designs to be assessed independently, without any intrusion into their place and route characteristics. We have studied implications of framework's intrusiveness into design under test by comparing proposed non-intrusive framework with previous intrusive methods; up to 5% deviation in the number of effective faults is observed in intrusive... 

    SCFIT: A FPGA-based fault injection technique for SEU fault model

    , Article Proceedings -Design, Automation and Test in Europe, DATE ; 2012 , Pages 586-589 ; 15301591 (ISSN) ; 9783981080186 (ISBN) Mohammadi, A ; Ebrahimi, M ; Ejlali, A ; Miremadi, S. G ; Sharif University of Technology
    2012
    Abstract
    In this paper, we have proposed a fast and easy-to-develop FPGA-based fault injection technique. This technique uses the Altera FPGAs debugging facilities in order to inject SEU fault model in both flip-flops and memory units. Since this method uses the FPGAs built-in facilities, it imposes a negligible performance and area overhead on the system. The experimental results on Leon2 processor shows that the proposed technique is on average four orders of magnitude faster than a simulation-based fault injection  

    Developing inherently resilient software against soft-errors based on algorithm level inherent features

    , Article Journal of Electronic Testing: Theory and Applications (JETTA) ; Vol. 30, issue. 2 , 2014 , p. 193-212 Arasteh, B ; Miremadi, S. G ; Rahmani, A. M ; Sharif University of Technology
    Abstract
    A potential peculiarity of software systems is that a large number of soft-errors are inherently derated (masked) at the software level. The rate of error-deration may depend on the type of algorithms and data structures used in the software. This paper investigates the effects of the underlying algorithms of programs on the rate of error-deration. Eight different benchmark programs were used in the study; each of them was implemented by four different algorithms, i.e. divide-and-conquer, dynamic, backtracking and branch-and-bound. About 10,000 errors were injected into each program in order to quantify and analyze the error-derating capabilities of different algorithm-designing- techniques.... 

    FPGA-based fault injection into synthesizable verilog HDL models

    , Article 2nd IEEE International Conference on Secure System Integration and Reliability Improvement, SSIRI 2008, Yokohama, 14 July 2008 through 17 July 2008 ; 2008 , Pages 143-149 ; 9780769532660 (ISBN) Shokrolah Shirazi, M ; Miremadi, S. G ; Sharif University of Technology
    2008
    Abstract
    This paper presents an FPGA-based fault injection tool, called FITO that supports several synthesizable fault models for dependability analysis of digital systems modeled by Verilog HDL. Using the FITO, experiments can be performed in real-time with good controllability and observability. As a case study, an OpenRISC 1200 microprocessor was evaluated using an FPGA circuit. About 4000 permanent, transient, and SEU faults were injected into this microprocessor. The results show that the FITO tool is more than 79 times faster than a pure simulation-based fault injection with only 2.5% FPGA area overhead. © 2008 IEEE  

    A software-based error detection technique using encoded signatures

    , Article 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Arlington, VA, 4 October 2006 through 6 October 2006 ; 2006 , Pages 389-397 ; 15505774 (ISSN); 076952706X (ISBN); 9780769527062 (ISBN) Sedaghat, Y ; Miremadi, S. G ; Fazeli, M ; Sharif University of Technology
    2006
    Abstract
    In this Paper, a software-based control flow checking technique called SWTES (Software-based error detection Technique using Encoded Signatures) is presented and evaluated. This technique is processor independent and can be applied to any kind of processors and microcontrollers. To implement this technique, the program is partitioned to a set of blocks and the encoded signatures are assigned during the compile time. In the run-time, the signatures are compared with the expected ones by a monitoring routine. The proposed technique is experimentally evaluated on an ATMEL MCS51 microcontroller using Software Implemented Fault Injection (SWIFI). The results show that this technique detects about... 

    Assessment of message missing failures in CAN-based systems

    , Article IASTED International Conference on Parallel and Distributed Computing and Networks, as part of the 23rd IASTED International Multi-Conference on Applied Informatics, Innsbruck, 15 February 2005 through 17 February 2005 ; 2005 , Pages 387-392 ; 10272666 (ISSN) Salmani, H ; Miremadi, S. G ; Fahringer T ; Hamza M. H ; Sharif University of Technology
    2005
    Abstract
    This paper presents a simulation-based environment to study fault effects in message missing failures in CAN-based systems. A CAN controller is modeled by VHDL at behavioral level and is exploited to set up a network composed of several nodes. A total of 27,000 transient faults of seven types are injected into five critical portions of the system including the bus and four portions of the CAN controller. The experimental results show that the faults affect the message sending in which more than 20% of faults cause the failure. Besides, with a heavy workload, faults that are occurred into the CAN controller and on the bus cause about 90% and 10% of all failures, respectively  

    Error detection enhancement in COTS superscalar processors with performance monitoring features

    , Article Journal of Electronic Testing: Theory and Applications (JETTA) ; Volume 20, Issue 5 SPEC.ISS , 2004 , Pages 553-567 ; 09238174 (ISSN) Rajabzadeh, A ; Miremadi, S. G ; Mohandespour, M ; Sharif University of Technology
    2004
    Abstract
    Increasing use of commercial off-the-shelf (COTS) superscalar processors in industrial, embedded, and real-time systems necessitates the development of error detection mechanisms for such systems. This paper presents an error detection scheme called Committed Instructions Counting (CIC) to increase error detection in such systems. The scheme uses internal Performance Monitoring features and an external watchdog processor (WDP). The Performance Monitoring features enable counting the number of committed instructions in a program. The scheme is experimentally evaluated on a 32-bit Pentium® processor using software implemented fault injection (SWIFI). A total of 8181 errors were injected into... 

    Investigation and reduction of fault sensitivity in the FlexRay communication controller registers

    , Article 27th International Conference on Computer Safety, Reliability, and Security, SAFECOMP 2008, Newcastle upon Tyne, 22 September 2008 through 25 September 2008 ; Volume 5219 LNCS , 2008 , Pages 153-166 ; 03029743 (ISSN); 3540876979 (ISBN); 9783540876977 (ISBN) Sedaghat, Y ; Miremadi, S. G ; Sharif University of Technology
    2008
    Abstract
    It is now widely believed that FlexRay communication protocol will become the de-facto standard for distributed safety-critical automotive systems. In this paper, the fault sensitivity of the FlexRay communication controller registers are investigated using transient single bit-flip fault injection. To do this, a FlexRay bus network, composed of four nodes, was modeled. A total of 135,600 transient single bit-flip faults were injected to all 408 accessible single-bit and multiple-bit registers of the communication controller in one node. The results showed that among all 408 accessible registers, 30 registers were immediately affected by the injected faults. The results also showed that... 

    Workload-aware Fault-injection for Speeding-up Evaluation of the Dependable Systems

    , M.Sc. Thesis Sharif University of Technology Javani Jananlu, Saeid (Author) ; Miremadi, Ghassem (Supervisor)
    Abstract
    Dependability assessment is an important preliminary in the design of dependable systems. Simulation Based Fault Injection (SBFI) is a common way to evaluate system dependability. To achieve high accuracy in SBFI, a large amount number of fault injection is required, which is very time consuming. Many of ideas are implied to solve this disadvantage of SBFI. In this work, we propose a method that uses information of workload execution on the processor to reduce faults to be injected during the SBFI campaign. We concentrate on Single Event Upsets because of its majority and repeating interval. Our proposed method first gathers information about various regions of the processor by probing... 

    An efficient technique to tolerate MBU faults in register file of embedded processors

    , Article CADS 2012 - 16th CSI International Symposium on Computer Architecture and Digital Systems ; 2012 , Pages 115-120 ; 9781467314824 (ISBN) Abazari, M. A ; Fazeli, M ; Patooghy, A ; Miremadi, S. G ; Sharif University of Technology
    2012
    Abstract
    This paper presents a Data Width-aware Register file Protection (DWRP) technique to cope with Multiple Bit Upsets (MBUs) occurring in the register file of embedded processors. The DWRP technique has been proposed based on the fact that there are often a significant number of bits in the register file, which are not fully occupied by data. The DWRP technique efficiently exploits these available free bits for reliability enhancement purposes. In this regard, every register is equipped with three extra tag bits to specify the amount of available free bits in a register. Then the appropriate parity or hamming code is used based on the information of the tag field to protect the register file... 

    FPGA-based Fault Injection for Evaluating the Fault Tolerance of Embedded Processors

    , M.Sc. Thesis Sharif University of Technology Mohammadi, Abbas (Author) ; Ejlali, Alireza (Supervisor)
    Abstract
    One the most important issues in most of embedded systems is reliability and fault tolerance.Ensure of correct operation and evaluate reliability and fault tolerance of embedded proces-sors as a critical part of embedded systems, would be necessary. Fault injection is one themostly used methods for evaluating those features. Using FPGA devices is a good alterna-tive for time consuming simulation-based fault injection method because of their speed. But,there are some critical issues in FPGA-based fault injection methods which are controllabil-ity and observability. In addition to need for efficient and applicable observation and controlmechanism to handle fault injection experiments, a... 

    Design and Evaluation of a Master/Checker Method for an Embedded Processor

    , M.Sc. Thesis Sharif University of Technology Ebrahimi, Mojtaba (Author) ; Miremadi, Ghasem (Supervisor)
    Abstract
    Ever increasing applications of embedded systems have motivated the designers to pay special attention to the design requirements of such systems. Among embedded applications, safety-critical systems have high reliability requirements as failures in such systems may endanger human life or result in catastrophic consequences. Embedded processors as the computation cores of embedded systems are very crucial from reliability point of view. This is because; a failure in the processor most probably leads to a system failure. One effective way to protect embedded processors against environmental faults is to use system level fault-tolerant techniques such as Master/Checker (M/C) or Triple Modular... 

    Fault Modeling of Transient Faults in Embedded Processors

    , M.Sc. Thesis Sharif University of Technology Tajik, Hossein (Author) ; Ejlali, Alireza (Supervisor)
    Abstract
    Many embedded processors are used in harsh environments and their behavior should be investigated against the incidence of common faults. Fault Injection is a prevalent method to do this investigation. Simulation-based fault injection is one of the most prominent forms of fault injection. A fault model is required to do simulation-based fault injection. Simulated faults should have the most similarity to the real faults. Temperature variation and in the extreme case thermal shock is one of the probable faults in harsh environment. In this thesis, we want to propose fault models for thermal shock in various abstraction levels, evaluate and compare these fault models and present methods to use... 

    Soft error rate estimation of digital circuits in the presence of Multiple Event Transients (METs)

    , Article Proceedings -Design, Automation and Test in Europe, DATE, 14 March 2011 through 18 March 2011 ; March , 2011 , Pages 70-75 ; 15301591 (ISSN) ; 9783981080179 (ISBN) Fazeli, M ; Ahmadian, S. N ; Miremadi, S. G ; Asadi, H ; Tahoori, M. B ; Sharif University of Technology
    2011
    Abstract
    In this paper, we present a very fast and accurate technique to estimate the soft error rate of digital circuits in the presence of Multiple Event Transients (METs). In the proposed technique, called Multiple Event Probability Propagation (MEPP), a four-value logic and probability set are used to accurately propagate the effects of multiple erroneous values (transients) due to METs to the outputs and obtain soft error rate. MEPP considers a unified treatment of all three masking mechanisms i.e., logical, electrical, and timing, while propagating the transient glitches. Experimental results through comparisons with statistical fault injection confirm accuracy (only 2.5% difference) and... 

    Fault injection in mixed-signal environment using behavioral fault modeling in Verilog-A

    , Article Proceedings of the IEEE International Workshop on Behavioral Modeling and Simulation, BMAS, 23 September 2010 through 24 September 2010, San Jose, CA ; September , 2010 , Pages 69-74 ; 21603804 (ISSN) ; 9781424489954 (ISBN) Ahmadian, S. N ; Miremadi, S. G ; Sharif University of Technology
    2010
    Abstract
    Fault injection methods have been used for analyzing dependability characteristics of systems for years. In this paper we propose a practical mixed-signal fault injection flow that is fast as well as accurate. We described three classes of most common faults: i) Single event transients, ii) Electro-Magnetic interference and iii) Power disturbance faults. Fault models are implemented directly into circuit's devices using behavioral fault description in Verilog-A language. As an example for dependability evaluation, some test circuits have been prepared and the results of fault injection on their designs have been reported  

    Fault effects in FlexRay-based networks with hybrid topology

    , Article ARES 2008 - 3rd International Conference on Availability, Security, and Reliability, Proceedings, 4 March 2008 through 7 March 2008, Barcelona ; 2008 , Pages 491-496 ; 0769531024 (ISBN); 9780769531021 (ISBN) Dehbashi, M ; Lari, V ; Miremadi, S. G ; Shokrollah Shirazi, M ; Sharif University of Technology
    2008
    Abstract
    This paper investigates fault effects and error propagation in a FlexRay-based network with hybrid topology that includes a bus subnetwork and a star subnetwork "The investigation is based on about 43500 bit-flip fault injection inside different parts of the FlexRay communication controller. To do this, a FlexRay communication controller is modeled by Verilog HDL at the behavioral level. Then, this controller is exploited to setup a FlexRay-based network composed of eight nodes (four nodes in the bus subnetwork and four nodes in the star subnetwork). The faults are injected in a node of the bus subnetwork and a node of the star subnetwork of the hybrid network. Then, the faults resulting in... 

    Control-flow checking using branch instructions

    , Article 5th International Conference on Embedded and Ubiquitous Computing, EUC 2008, Shanghai, 17 December 2008 through 20 December 2008 ; Volume 1 , January , 2008 , Pages 66-72 ; 9780769534923 (ISBN) Jafari Nodoushan, M ; Miremadi, S. G ; Ejlali, A ; IEEE Computer Society Technical Committee on Scalable Computing ; Sharif University of Technology
    2008
    Abstract
    This paper presents a hardware control-flow checking scheme for RISC processor-based systems. This Scheme combines two error detection mechanisms to provide high coverage. The first mechanism uses parity bits to detect faults occurring in the opcodes and in the target addresses of branch instructions which lead to erroneous branches. The second mechanism uses signature monitoring to detect errors occurring in the sequential instructions. The scheme is implemented using a watchdog processor for an VHDL model of the LEON2 processor. About 31800 simulation faults were injected into the LEON2 processor. The results show that the error detection coverage is about 99.5% with average detection... 

    Error propagation analysis using FPGA-based SEU-fault injection

    , Article Microelectronics Reliability ; Volume 48, Issue 2 , 2008 , Pages 319-328 ; 00262714 (ISSN) Ejlali, A ; Miremadi, S. G ; Sharif University of Technology
    2008
    Abstract
    Error propagation analysis is one of the main objectives of fault injection experiments. This analysis helps designers to detect design mistakes and to provide effective mechanisms for fault tolerant systems. However, error propagation analysis requires that the chosen fault injection technique provides a high degree of observability (i.e., the ability to observe the internal values and events of a circuit after a fault is injected). Simulation-based fault injection provides a high observability adequate for error propagation analysis. However, the performance of the simulation-based technique is inadequate to handle today's hardware complexity. As an alternative, FPGA-based fault injection... 

    Dependability evaluation of Altera FPGA-based embedded systems subjected to SEUs

    , Article Microelectronics Reliability ; Volume 47, Issue 2-3 , 2007 , Pages 461-470 ; 00262714 (ISSN) Zarandi, H. R ; Miremadi, S. G ; Sharif University of Technology
    2007
    Abstract
    Dependability evaluation of embedded systems due to the integration of hardware and software parts is difficult to analyze. In this paper, we have proposed an experimental method to determine sensitivity to soft errors in an embedded system exploiting Altera SRAM-based FPGAs. The evaluation is performed using both the hardware and software parts of the embedded system in a single framework. To do this, the HDL hardware model of the target system as well as the C-written software codes of the target system, are required. Both permanent and transient faults are injected into the partially- or fully-synthesizable hardware of the target system and this can be performed during the design cycle of... 

    Evaluation of babbling idiot failures in FlexRay-based networkes

    , Article IFAC Proceedings Volumes (IFAC-PapersOnline) ; Volume 7, Issue PART 1 , 2007 , Pages 399-406 ; 14746670 (ISSN); 9783902661340 (ISBN) Lari, V ; Dehbashi, M ; Miremadi, S. G ; Amiri, M ; Sharif University of Technology
    IFAC Secretariat  2007
    Abstract
    This paper evaluates the error propagation and its effects in babbling idiot failure in a FlexRay-based network. The evaluation is based on about 35680 bit-flip fault injections inside different parts of the FlexRay communication controller. To do this, a FlexRay communication controller is modeled by Verilog HDL at the behavioral level. Then, this controller is exploited to setup a FlexRay-based network composed of four nodes. Nodes in this experiment are considered in two forms: 1) node without bus guardian, 2) node with bus guardian. The results of fault injection show that in first form about 4.57% of faults lead to the babbling idiot failures. Also in second form about 0.75% faults lead...