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    Functional fault model definition for bus testing

    , Article Proceedings of IEEE East-West Design and Test Symposium, EWDTS 2013, Rostov-on-Don ; 2013 ; 9781479920969 (ISBN) Karimi, E ; Haghbayan, M. H ; Maleki, A ; Tabandeh, M ; Sharif University of Technology
    In this paper we present a new fault model for testing bus components using their functionality. With the aim of a new fault model definition all components in a bus except cores of the SoC will be tested as fast as possible. According to the proposed method in this paper, at first, wires and small components will be tested by marching test patterns as the test data and, after that based on a proposed method; the new format faults for the bus will be used. Using AMBA-AHB as the experimental result, the new fault model shows efficiency in comparison with corresponding stuck-at  

    Fault injection in mixed-signal environment using behavioral fault modeling in Verilog-A

    , Article Proceedings of the IEEE International Workshop on Behavioral Modeling and Simulation, BMAS, 23 September 2010 through 24 September 2010, San Jose, CA ; September , 2010 , Pages 69-74 ; 21603804 (ISSN) ; 9781424489954 (ISBN) Ahmadian, S. N ; Miremadi, S. G ; Sharif University of Technology
    Fault injection methods have been used for analyzing dependability characteristics of systems for years. In this paper we propose a practical mixed-signal fault injection flow that is fast as well as accurate. We described three classes of most common faults: i) Single event transients, ii) Electro-Magnetic interference and iii) Power disturbance faults. Fault models are implemented directly into circuit's devices using behavioral fault description in Verilog-A language. As an example for dependability evaluation, some test circuits have been prepared and the results of fault injection on their designs have been reported  

    Graph based fault model definition for bus testing

    , Article IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC, Istanbul ; October , 2013 , Pages 54-55 ; 23248432 (ISSN) ; 9781479905249 (ISBN) Karimi, E ; Haghbayan, M. H ; Maleki, A ; Tabandeh, M ; Sharif University of Technology
    IEEE Computer Society  2013
    In this paper we present a new fault model for testing standard On-Chip buses using a graph model. This method will be optimized for speed of testing. Using AMBA-AHB as the experimental result, the proposed fault model shows efficiency in comparison with corresponding stuck-At fault testing  

    Accelerated on-chip communication test methodology using a novel high-level fault model

    , Article Proceedings - IEEE 9th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2015, 23 September 2015 through 25 September 2015 ; 2015 , Pages 283-288 ; 9781479986699 (ISBN) Karimi, E ; Haghbayan, M. H ; Rahmani, A. M ; Tabandeh, M ; Liljeberg, P ; Navabi, Z ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2015
    A novel high-level fault model to accelerate test process of on-chip communication structures for SoCs is proposed. To this end, bus components are modeled using a simple, yet efficient, graph-based technique and all possible faults on the graph nodes are probed. The proposed method is optimized in terms of test time. The method applies the same test process to all interconnects and components. Compared to the conventional stuck-at fault testing methods, our extensive simulations on the AMBA-AHB bus architecture reveal that our test method can help in achieving a significant test speed improvement  

    Improvement of fault detection in wireless sensor networks

    , Article 2009 Second ISECS International Colloquium on Computing, Communication, Control, and Management, CCCM 2009, Sanya, 8 August 2009 through 9 August 2009 ; Volume 4 , 2009 , Pages 644-646 ; 9781424442461 (ISBN) Khazaei, E ; Barati, A ; Movaghar, A ; Yangzhou University; Guangdong University of Business Studies; Wuhan Institute of Technology; IEEE SMC TC on Education Technology and Training; IEEE Technology Management Council ; Sharif University of Technology
    This paper presents a centralized fault detection algorithm for wireless sensor networks. Faulty sensor nodes are identified based on comparisons between neighboring nodes and own central node and dissemination of the decision made at each node. RNS system is used to tolerate transient faults in sensing and communication. In this system, arithmetic operations act on residues - reminder of dividing original number in several definite modules - in parallel. Consequently computations on these residues which are smaller than the original number are performed, so speed up arithmetic and decreased power consumption is achieved. ©2009 IEEE  

    Design and Implementation of a GAIT Analysis System Using Kinect for Clinical Application

    , M.Sc. Thesis Sharif University of Technology Jamali Soosefi, Zahra (Author) ; Behzadipour, Saeed (Supervisor)
    To date various commercial systems were used in the gait analysis area. These systems have some difficulties for clinical use, such as being indwell, making trouble in movement and high prices. The Kinect sensor does not have problems of these systems. If the error of sensor is acceptable, Kinect sensor is a suitable choice for application in clinics. The possibility of utilization of the Kinect sensor as a gait analysis system has been studied in this research. The sensor errors in calculation of gait parameters such as lower limb joints angle, stride time, stride length and spatial coordinates of joints were computed. In previous researches the Kinect sensor error has been calculated for... 

    SCFIT: A FPGA-based fault injection technique for SEU fault model

    , Article Proceedings -Design, Automation and Test in Europe, DATE ; 2012 , Pages 586-589 ; 15301591 (ISSN) ; 9783981080186 (ISBN) Mohammadi, A ; Ebrahimi, M ; Ejlali, A ; Miremadi, S. G ; Sharif University of Technology
    In this paper, we have proposed a fast and easy-to-develop FPGA-based fault injection technique. This technique uses the Altera FPGAs debugging facilities in order to inject SEU fault model in both flip-flops and memory units. Since this method uses the FPGAs built-in facilities, it imposes a negligible performance and area overhead on the system. The experimental results on Leon2 processor shows that the proposed technique is on average four orders of magnitude faster than a simulation-based fault injection  

    Phase-change memory architectures

    , Article Advances in Computers ; Volume 118 , 2020 , Pages 29-48 Asadinia, M ; Sarbazi Azad, H ; Sharif University of Technology
    Academic Press Inc  2020
    Some of the recent approaches regarding leverage PCM will be reviewed in this chapter. The chapter starts with a discussion regarding future main memory systems that includes hybrid architecture schemes using both PCM and DRAM arrays. Later, we focus on PCM only approaches and this section will help describe some techniques for reducing the increased read latency because of slow writes in PCMs. In this chapter, we also illustrate wear-leveling approaches and review the security problems of this memory approach which are lifetime limited. This section includes an overview of the recent security aware wear-leveling techniques, whose methods help detect attacks, and their issues during the... 

    System Level Communication Testing Considering Functionality

    , M.Sc. Thesis Sharif University of Technology Karimi, Elmira (Author) ; Tabandeh, Mahmoud (Supervisor) ; Navabi, Zainalabedin (Co-Advisor)
    Due to the development of electronics, technology has entered new levels of integration on a single chip, called the System-on-Chip (SoC) design. Currently a SoC may contain various Intellectual Property (IP) cores with different interface protocols. For typical SoC communication, designers implement numerous standards such as Avalon from Altera and AMBA from ARM. These standards have different topologies with their own properties and are suitable for specific applications, But the challengeable problem is testing interconnects between cores. In testing process, important elements of a bus that should be tested are interconnections between cores (wires), multiplexers, arbiters, decoders, and... 

    Fault Modeling of Transient Faults in Embedded Processors

    , M.Sc. Thesis Sharif University of Technology Tajik, Hossein (Author) ; Ejlali, Alireza (Supervisor)
    Many embedded processors are used in harsh environments and their behavior should be investigated against the incidence of common faults. Fault Injection is a prevalent method to do this investigation. Simulation-based fault injection is one of the most prominent forms of fault injection. A fault model is required to do simulation-based fault injection. Simulated faults should have the most similarity to the real faults. Temperature variation and in the extreme case thermal shock is one of the probable faults in harsh environment. In this thesis, we want to propose fault models for thermal shock in various abstraction levels, evaluate and compare these fault models and present methods to use... 

    An extended component-based reliability model for protective systems to determine routine test schedule

    , Article Turkish Journal of Electrical Engineering and Computer Sciences ; Volume 19, Issue 2 , March , 2011 , Pages 303-315 ; 13000632 (ISSN) Abbarin, A ; Firuzabad, M. F ; Ozdemir, A ; Sharif University of Technology
    This paper presents a novel approach for evaluating the reliability of protective systems taking into account its components reliability. In this paper, a previously proposed extended model is used for a directional over- current scheme. In the extended model, the impacts of individual protective components are taken into account. An optimum routine test schedule is determined for each protective component as a separate unit. A comparison is made to show that the proposed approach has excellence over conventional routine test inspections. Impacts of factors such as circuit breaker inadvertent opening, required time for performing routine test inspections, human mistakes and self-checking and... 

    Model based compressor fault identification using stage stacking technique and nonlinear diagnostic systems

    , Article Proceedings of the ASME Turbo Expo, 9 June 2008 through 13 June 2008, Berlin ; Volume 2 , 2008 , Pages 213-221 ; 9780791843123 (ISBN) Hosseini, H. R ; Khaledi, H ; Ghofrani, M. B ; International Gas Turbine Institute ; Sharif University of Technology
    Compressor fault identification is an important part of gas turbine diagnostic systems. Model based techniques have been used widely in this field. In this paper the performance of two compressors has been simulated using stage stacking method. One of them is the NASA 10 stage constant tip diameter compressor. The other one is the Siemens V94.2 engine's compressor. Then a new and more real compressor fault model is introduced and the effect of different faults on compressor performance has been studied. In this paper an intelligent fault diagnostic system has been developed which is able to detect different faults of the compressor. In all of the cases of faults, degradation in inlet flow... 

    Estimation of stress drop for some large shallow earthquakes using stochastic point source and finite fault modeling

    , Article Scientia Iranica ; Volume 17, Issue 3 A , JUNE , 2010 , Pages 217-235 ; 10263098 (ISSN) Moghaddam, H ; Fanaie, N ; Motazedian, D ; Sharif University of Technology
    Using stochastic point source and finite fault modeling, the stochastic stress drop is estimated for 52 large shallow earthquakes listed in the 'Pacific Earthquake Engineering Research Center (PEER) Next Generation Attenuation of Ground Motions (NGA)' database. The Pseudo Spectral Acceleration (PSA) of 541 accelerograms, recorded at National Earthquake Hazards Reduction Program (NEHRP) C-class sites from 52 earthquakes are simulated and compared with the PSA listed in the PEER NGA database. The magnitude of the analyzed earthquakes ranged from M4:4 to M7:6. The stress drop is calibrated by trial and error and based on the analysis of residuals where the residual is defined as the log of the... 

    Improving the Training Process of Understanding Unit in Spoken Dialog Systems Using Active Learning Methods

    , M.Sc. Thesis Sharif University of Technology Hadian, Hossein (Author) ; Sameti, Hossein (Supervisor)
    This thesis aims at reducing the need for labeled data in the SLU domain by the means of active Learning methods. This need is due to the lack of labeled datasets for Spoken Language Understanding (SLU) in the Persian language, and fairly high labeling costs. Active learning methods enables the learner to choose the most informative instances to be labeled and used for training, and prevents labeling uninformative or redundant instances. For modeling the SLU system, several statistical models namely MLN (Markov Logic Networks), CRF (Conditional Random Fields), HMM (Hidden Markov Model) and HVS (Hidden Vector State) were reviewed, and finally CRF was chosen for its superior performance. The... 

    Reliability Improvement in Non-Volatile On-Chip Memories for Embedded Applications

    , Ph.D. Dissertation Sharif University of Technology Hosseini Monazzah, Amir Mahdi (Author) ; Miremadi, Ghassem (Supervisor)
    With the technology scaling trend in recent years, leakage power has become a major challenge for SRAM-based on-chip memories. According to the recent reports, SRAM-based on-chip memories contribute to more than half of the processors’ power consumption. Accordingly, in recent years, researchers have tried to find an alternative technology for SRAMs in on-chip memories. The International Technology Roadmap for Semiconductors (ITRS) recently announced that STT-MRAMs are the most promising technology to replace SRAMs. While STT-MRAMs benefit from low energy consumption, high endurance, and high density compared to other non-volatile memory technologies, comparing with SRAMs, STT-MRAMs have... 

    Feature specific control flow checking in COTS-based embedded systems

    , Article Proceedings - 3rd International Conference on Dependability, DEPEND 2010, 18 July 2010 through 25 July 2010 ; July , 2010 , Pages 58-63 ; 9780769540900 (ISBN) Rajabzadeh, A ; Miremadi, S.G ; IARIA ; Sharif University of Technology
    While the Control Flow Checking (CFC) methods are using the ordinary instruction set and general Arithmetic and Logic Unit (ALU) features to protect the programs against the transient faults, this paper presents a new kind of CFC method, called feature specific CFC. The idea behind this method is using a specific internal hardware in modern processors which provides the ability to monitor internal various parameters of the program. This method is a pure software method and the external hardware overhead is zero. Other overheads have been measured experimentally by executing the workloads on a Pentium system. The execution time overhead is between 42% and 67% and the program size overhead is... 

    ACM: Accurate crosstalk modeling to predict channel delay in Network-on-Chips

    , Article 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design, IOLTS 2016, 4 July 2016 through 6 July 2016 ; 2016 , Pages 7-8 ; 9781509015061 (ISBN) Mahdavi, Z ; Shirmohammadi, Z ; Miremadi, S. G ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2016
    The severity of timing delay in the communication channels of Network on Chip (NoC) depends on the transition patterns appearing on the wires. An analytical model can estimate the timing delay in NoC channels in the presence of crosstalk faults. However, recently proposed analytical model does not have enough accuracy and is based on 3-wire delay model. In this paper, an Accurate Crosstalk Model (ACM) based on 5-wire delay model is proposed to estimate the delay of communication channels in the presence of crosstalk faults. ACM is more accurate due to considering more wires in the delay model and also considering the overlaps between locations of transition patterns  

    Guest editorial special section on microgrids

    , Article IEEE Transactions on Smart Grid ; Volume 3, Issue 4 , December , 2012 , Pages 1857-1859 ; 19493053 (ISSN) Fotuhi Firuzabad, M ; Iravani, R ; Aminifar, F ; Hatziargyriou, N ; Lehtonen, M ; Sharif University of Technology
    Despite the significant research efforts devoted to the microgrid and smart grid areas, numerous problems related to real world implementations still remain unsolved. The present special issue was announced with the objective of addressing and disseminating state-of-the-art R&D results on microgrids to bring together researchers from both academia and industry with the goal of fostering interactions among stakeholders. In response, 190 two-page extended abstracts were received and considered for the first round of reviews. Authors of about 60 selected abstracts were then invited to submit the full papers in the second round and out of them 27 high-quality manuscripts were ultimately approved... 

    AM3D: An accurate crosstalk probability modeling to predict channel delay in 3D ICs

    , Article Microelectronics Reliability ; Volume 102 , 2019 ; 00262714 (ISSN) Shirmohammadi, Z ; Nikoofard, A ; Ershadi, G ; Sharif University of Technology
    Elsevier Ltd  2019
    Migration from Two Dimensional Integrated Circuits (2D ICs) to Three Dimensional Integrated Circuits (3D ICs) reduces the delay due to the shorter wire length between sender and receiver. However, Through-Silicon-Vias (TSVs) that connect layers in the structure of 3D ICs can seriously increase the delay due to capacitance coupling between TSVs and lead to crosstalk fault. The severity of crosstalk faults depends on transitions appearing on TSVs that is called transition patterns. To propose an efficient crosstalk tackling mechanisms in 3D ICs, an accurate probability analytical model is required to predict the delay caused by TSVs (3D ICs) in the attendance of these transition patterns. In... 

    Uniform hazard response spectra and ground motions for tabriz

    , Article Scientia Iranica ; Volume 16, Issue 3 , 2009 , Pages 238-248 ; 10263098 (ISSN) Moghaddam, H ; Fanaie, N ; Hamzehloo, H ; Sharif University of Technology
    Tabriz has experienced several large destructive historical earthquakes in the past. Due to the absence of ground motion records in this area, a simulation of future events based on a regional seismicity information and ground motion model is necessary. Based on a maximum likelihood method, earthquake magnitude is estimated for a 10% probability of exceedance within 50 years (475-year return period) and its corresponding strong ground motions have been simulated using stochastic finite fault modeling. Using different stress parameters, suites of ground motions have been simulated for a return period of £75 years and their spectral accelerations have been compared with the corresponding...