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    Reactor modeling of direct conversion of methane to methanol in a catalytic fluidized bed reactor

    , Article CHISA 2006 - 17th International Congress of Chemical and Process Engineering, Prague, 27 August 2006 through 31 August 2006 ; 2006 ; 8086059456 (ISBN); 9788086059457 (ISBN) Vafajoo, L ; Ghods, M ; Kazemeini, M ; Sharif University of Technology
    2006
    Abstract
    Direct conversion of methane to methanol is a more recently developed technique by which the intermediate and expensive process of formation of synthesis gas is eliminated. On the other hand, fluidized-bed technology for heterogeneous reversible reactions posses a couple of key advantages in comparison to the commonly used fixed bed reactors. These include, pore diffusion resistances being largely eliminated due to small catalyst pellet sizes utilized. In other words, industrial fixed bed pellets are in the order of 6-12 mm diameter, whereas fluidized catalyst used may be smaller than 100 μm. In addition, equilibrium limitations induced by the reversibility of the reaction(s) are broken in... 

    Power-performance analysis of networks-on-chip with arbitrary buffer allocation schemes

    , Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ; Vol. 29, issue. 10 , 2010 , p. 1558-1571 ; ISSN: 02780070 Arjomand, M ; Sarbazi-Azad, H ; Sharif University of Technology
    Abstract
    End-to-end delay, throughput, energy consumption, and silicon area are the most important design metrics of networks-on-chip (NoCs). Although several analytical models have been previously proposed for predicting such metrics in NoCs, very few of them consider the effect of message waiting time in the buffers of network routers for predicting overall power consumptions and none of them consider structural heterogeneity of network routers. This paper introduces two inter-related analytical models to compute message latency and power consumption of NoCs with arbitrary topology, buffering structure, and routing algorithm. Buffer allocation scheme defines the buffering space for each individual... 

    Power-performance analysis of networks-on-chip with arbitrary buffer allocation schemes

    , Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ; Volume 29, Issue 10 , September , 2010 , Pages 1558-1571 ; 02780070 (ISSN) Arjomand, M ; Sarbazi Azad, H ; Sharif University of Technology
    2010
    Abstract
    End-to-end delay, throughput, energy consumption, and silicon area are the most important design metrics of networks-on-chip (NoCs). Although several analytical models have been previously proposed for predicting such metrics in NoCs, very few of them consider the effect of message waiting time in the buffers of network routers for predicting overall power consumptions and none of them consider structural heterogeneity of network routers. This paper introduces two inter-related analytical models to compute message latency and power consumption of NoCs with arbitrary topology, buffering structure, and routing algorithm. Buffer allocation scheme defines the buffering space for each individual... 

    A low power error detection technique for floating-point units in embedded applications

    , Article 5th International Conference on Embedded and Ubiquitous Computing, EUC 2008, Shanghai, 17 December 2008 through 20 December 2008 ; Volume 1 , January , 2008 , Pages 199-205 ; 9780769534923 (ISBN) Shekarian, M. H ; Ejlali, A ; Miremadi, S. G ; IEEE Computer Society Technical Committee on Scalable Computing ; Sharif University of Technology
    2008
    Abstract
    Reliability and low power consumption are two major design objectives in today's embedded systems. Since floating-point units (FPU) are required for some embedded applications (e.g., multimedia applications), careful considerations should be given to the reliability and power consumptions of FPUs used in embedded systems. When using existing fault handling mechanisms for FPUs, it has been observed that the division operation imposes a considerable hardware overhead as compared to the addition, subtraction, and multiplication operations. Although the division operation is less frequently used, in reliable applications it is a must that all the components operate properly. In this paper, we... 

    Effect of anode compositions on the current efficiency of zinc electrowinning

    , Article Proceedings - European Metallurgical Conference, EMC 2011 ; Volume 2 , 2011 , Pages 387-396 ; 9783940276377 (ISBN) Dashti, S ; Rashchi, F ; Vahidi, E ; Emami, M ; Khoshnevisan, A ; Sharif University of Technology
    Abstract
    The main goals in zinc electrowinning process are decreasing of power consumption and increasing of current efficiency. The purpose of this research was to investigate effect of different alloy compositions used in production of lead-based anodes on the zinc electrowinning process. The anode compositions prepared and examined in this study were binary alloys Pb - (0.5 and 2 %) Ag and quaternary alloys Pb - 0.5 % Ag - 1 % Ca - 2 % Sn, Pb - 0.5 % Ag - 1 % Ca - 1 % Sn - 1 % Sb and Pb - 0.5 % Ag - 1 % Ca - 1 % Sn - 1 % Bi. The electrowinning experiments were conducted using a laboratory-scale apparatus, at a plating time of 4 hours, a current density of 500 to 1000 A/m2, industrial zinc sulfate... 

    An efficient DVS scheme for on-chip networks using reconfigurable Virtual Channel allocators

    , Article Proceedings of the International Symposium on Low Power Electronics and Design, 22 July 2015 through 24 July 2015 ; Volume 2015-September , July , 2015 , Pages 249-254 ; 15334678 (ISSN) ; 9781467380096 (ISBN) Sadrosadati, M ; Mirhosseini, A ; Aghilinasab, H ; Sarbazi Azad, H ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2015
    Abstract
    Network-on-Chip (NoC) is a key element in the total power consumption of a chip multiprocessor. Dynamic Voltage Scaling is a promising method for power saving in NoCs since it contributes to reduction in both static and dynamic power consumptions. In this paper, we propose a novel scheme to reduce on-chip network power consumption when the number of Virtual Channels (VCs) with active allocation requests per cycle is less than the number of total VCs. In our method, we introduce a reconfigurable arbitration logic which can be configured to have multiple latencies and hence, multiple slack times. The increased slack times are then used to reduce the supply voltage of the routers in order to... 

    Synthesis and elucidation of electrochemical characteristics of nanorods, microsized and nanosized CuO as cathode materials for Zn/CuO alkaline battery

    , Article Journal of Solid State Electrochemistry ; Volume 19, Issue 7 , April , 2015 , Pages 2155-2165 ; 14328488 (ISSN) Zeraatkish, Y ; Jafarian, M ; Gobal, F ; Mahjani, M. G ; Sharif University of Technology
    Springer New York LLC  2015
    Abstract
    Discharge characteristics of nanorods (NRs), microsized and nanosized copper (II) oxide (CuO) particles prepared via thermal decomposition and thermal oxidation routes are examined as cathode materials of a Zn/CuO cell without membrane separators. The electrochemical discharge is examined galvanostatically at a current density of 500 mAg−1 and reveals that the first discharge cycles of all the CuO materials contain one potential plateau; subsequent discharge cycles involve three potential plateaus. Each potential plateau is due to an electrochemical reaction. The first, second, and third potential plateaus are attributed to Cu2O3, CuO, and Cu2O discharges,... 

    Addressing NoC reliability through an efficient fibonacci-based crosstalk avoidance codec design

    , Article Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 18 November 2015 through 20 November 2015 ; Volume 9530 , 2015 , Pages 756-770 ; 03029743 (ISSN); 9783319271361 (ISBN) Shirmohammadi, Z ; Miremadi, S. G ; Wang, G ; Perez, G. M ; Zomaya, A ; Li, K ; Sharif University of Technology
    Springer Verlag  2015
    Abstract
    The reliable transfer in Network on Chips (NoCs) can be threatened by crosstalk fault occurring in wires. Crossstalk fault is due to inter-wire coupling capacitance that based on the patterns of transitions appearing on the wires, significantly limits the reliability of NoCs. Among these transitions, 101 and 010 bit patterns impose the worst crosstalk effects to wires. This work intends to increase the reliability of NoCs against crosstalk faults by applying an improved Fibonacci-based numeral system, called Doubled-Penultimate Fibonacci (DP-Fibo). In the DP-Fibo coding algorithm, code words without ‘101’ and ‘010’ bit patterns are produced to reduce crosstalk faults. Experimental results... 

    Analytical leakage/temperature-aware power modeling and optimization for a variable speed real-time system

    , Article ACM International Conference Proceeding Series ; 2012 , Pages 81-90 ; 9781450314091 (ISBN) Mohaqeqi, M ; Kargahi, M ; Movaghar, A ; Sharif University of Technology
    2012
    Abstract
    We consider a DVS-enabled single-processor firm real-time (FRT) system with Poisson arrival jobs having exponential execution times and generally distributed relative deadlines. The queue size of the system bounds the number of jobs which may be available therein. Further, the processor speed depends on the number of jobs in the system which varies because of the job arrivals, service completions, and dead-line misses. Thus, the processor power consumption, includling both the dynamic and leakage powers, depends on the stochastic nature of the system. More specifically, the instantaneous dynamic power consumption lonely depends on the number of jobs at that moment. However, the instantaneous...