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fpga-based-implementation
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Networked adaptive non-linear oscillators: A digital synthesis and application
, Article Circuits, Systems, and Signal Processing ; Vol. 34, Issue. 2 , 2014 , pp. 483-512 ; ISSN: 1531-5878 ; Ahmadi, A ; Makki, S. V. A. - D ; Soleimani, H ; Bavandpour, M ; Sharif University of Technology
Abstract
This paper presents a digital hardware implementation of a frequency adaptive Hopf oscillator along with investigation on systematic behavior when they are coupled in a population. The mathematical models of the oscillator are introduced and compared in sense of dynamical behavior by using system-level simulations based on which a piecewise-linear model is developed. It is shown that the model is capable to be implemented digitally with high efficiency. Behavior of the oscillators in different network structures to be used for dynamic Fourier analysis is studied and a structure with more precise operation which is also more efficient for FPGA-based implementation is implemented. Conceptual...
Finite state machine based countermeasure for cryptographic algorithms
, Article 2017 14th International ISC (Iranian Society of Cryptology) Conference on Information Security and Cryptology, ISCISC 2017, 6 September 2017 through 7 September 2017 ; 2018 , Pages 58-63 ; 9781538665602 (ISBN) ; Rezaei Shahmirzadi, A ; Salmasizadeh, M ; Gholampour, I ; Sharif University of Technology
Abstract
In this work, we present a novel FPGA-based implementation of the AES algorithm which has a two-layered resistance against power analysis attacks. Our countermeasure is based on the concept of finite state machine equipped with a random number generator. Beyond masking the intermediate variables as the first layer of defense, we randomize the sequences of operations and add dummy computations as the second layer of defense. Therefore, the first order attack is prevented and the number of power traces needed for a successful second order attack is vastly increased and the correlation coefficient is decreased, as expected. © 2017 IEEE
An FPGA based implementation of G.729
, Article IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005, Kobe, 23 May 2005 through 26 May 2005 ; 2005 , Pages 3571-3574 ; 02714310 (ISSN) ; Vahdat, B ; Radfar, M. H ; Sharif University of Technology
2005
Abstract
Main objective of this article is to present the implementation and simulation of a Conjugate Structure Algebraic Code Excited Linear Prediction speech coder (CSACELP) based upon ITU-T's G.729 recommendation and to optimize it for real-time implementation on an FPGA. The suggested architecture is characterized by pipelining and parallel operation of functional units; using fixed point two's complement representation for integers. The design was functionally verified by utilizing the ModelSim software package from Mentor Graphics Corporation Company and then synthesized by Xilinx Integrated Software Environment (ISE) 6.1 software. Preliminary results show that the overall system delay is less...