Sharif Digital Repository

The most challenging issue of conventional Time Amplifiers (TAs) is their limited Dynamic Range (DR). This paper presents a mathematical analysis to clarify principle of operation of conventional 2× TA's. The mathematical derivations release strength reduction of the current sources of the TA is the simplest way to increase DR. Besides, a new technique is presented to expand the Dynamic Range (DR) of conventional 2× TAs. Proposed technique employs current subtraction in place of changing strength of current sources using conventional gain compensation methods, which results in more stable gain over a wider DR. The TA is simulated using Spectre-rf in TSMC 0.18um COMS technology. DR of the 2×... 

A new nonlinear Time to Digital Converter (TDC) based on time difference amplification is the proposed. A new gain compensation method is presented to expand the DR of conventional × 2 Time Amplifiers (TAs). Instead of conventional gain compensation approach based on changing strength of current sources, the proposed technique uses current difference which results more stable gain over wider DR. In order to avoid two different paths of the stages, a sign bit detection part is the proposed at the front of the TDC to allow using one path of stages for both positive and negative input time differences. As a result, the most advantages of the proposed TDC are its high resolution, wide DR, and... 

In this paper, a new simple and complete technique of modeling and analysis of a matrix converter is presented based on the singular value decomposition (SVD) of modulation matrix. The proposed modeling method yields a new limitation between the matrix converter gain and its input power factor, which is more relaxed as compared to the limits reported so far in the literature. The SVD of the modulation matrix leads to a unified modulation technique which achieves the full capability of a matrix converter. It is shown that this approach is general and all other modulation methods established for a matrix converter are specific cases of this technique. The proposed modulation method can be used... 

A new ultra wideband (UWB) pulse generator covering a-10 dB bandwidth of 2.4-4.6 GHz with a tunable center frequency of 5-5.6 GHz to mitigate coexistence issues of impulse radio UWB (IR-UWB) systems and IEEE802.11.a WLAN or other narrowband (NB) systems in 90 nm-CMOS technology is proposed. The UWB pulse is generated based on frequency up-conversion of the first derivative of the Gaussian pulse, which creates an adjustable null in the frequency spectrum. Simulation results show that employing the proposed pulse generator mitigates the mutual interference between UWB and WLAN systems, significantly. The proposed transmitter consists of a low frequency signal generator, an LC oscillator and a... 

Reduction of Time to Digital Converter (TDC) quantization related phase noise is one of the most important challenges in all digital frequency synthesizer design. In this paper, a new structure is proposed to shape the quantization noise of flash TDCs. To verify effectiveness of the proposed general noise shaping technique, it is employed on a single delay chain flash TDC. To compensate the process variation effects on the implemented circuits, a calibration technique is also proposed. The design is implemented in 0.18μm CMOS technology. Simulations show effective noise shaping of output quantization noise  

Time amplifiers (TA) are the key building blocks of the two-step time-to-digital converters. High resolution TAs suffer from inaccuracy the gain due to employing meta-stability behavior of the SR latches. In the proposed method, two offset NAND gates are placed in parallel with the NAND gates of the conventional SR latch to get a linear re-configurable gain. Gain of the TA is controlled only by the driving strength of the NAND gates. To confirm the effectiveness of the proposed method, an 8-bit two step time to digital converter (TDC) was designed and laid-out in 0.18 μ m CMOS technology. Using a supply voltage of 1.2V, the proposed TDC consumes 1.1mW at 30MS/s throughput. IEEE  

In this paper, a novel droop approach for autonomous power management in low voltage DC (LVDC) microgrids based on a master-slave concept is presented. Conventional voltage-based droop approaches suffer from poor power sharing due to line resistance effects on a virtual resistance, which is solved by introducing a communication system to increase the current sharing accuracy. In this paper, a virtual frequency is superimposed by the master units, and slave units determine their output power according to the corresponding frequency-based droop characteristics. Unlike the voltage-droop methods, the proposed virtual frequency-droop approach can be applied for proportional power management among... 

Microwave power modules are the result of integration of vacuum tubes and their respective power supplies. In these modules, volume and weight are very important factors because the modules are used in many portable applications. There are many parameters that they affect the volume and weight of the microwave power module. High voltage issues are one of these factors because the required voltages of vacuum tubes are high voltage. Thermal management relates to the module volume directly. In high-voltage high-frequency converters as power supplies of vacuum tubes, parasitic elements of the transformer are dominant. Tuning the transformer parameters leads to variation in the volume of the... 

Time amplifiers (TAs) are the key building blocks of the two-step time-to-digital converters. High resolution TAs suffer from inaccuracy the gain due to employing meta-stability behavior of the SR latches. In the proposed method, two offset NAND gates are placed in parallel with the NAND gates of the conventional SR latch to get a linear re-configurable gain. Gain of the TA is controlled only by the driving strength of the NAND gates. To confirm the effectiveness of the proposed method, an 8-bit two step time to digital converter (TDC) was designed and laid-out in 0.18- μm CMOS technology. Using a supply voltage of 1.2 V, the proposed TDC consumes 1.1 mW at 30 MS/s throughput. © 2004-2012... 

A Multi-level asynchronous delta sigma modulator consist of several Schmitt-triggers and a novel time-to-digital converter is presented as a core of a delta sigma modulation based analog to digital converter (ADC). The modulator firstly modulates the amplitude of its analog input signal to a multilevel asynchronous duty-cycle modulated signal. Then a time to digital converter (TDC) must be applied to generate digital representation of the received signal from the multi-level asynchronous duty-cycle modulated signal. A multi-level structure has been developed in this work while the prior works often used a single Schmitt. One of the most important limitations in conventional asynchronous... 

In this paper, we present and analyze a novel all-optical multilevel multiclass optical code division multiple access (OCDMA) system, using optical analog-to-digital converter (ADC) and advanced optical logic gate elements. In such OCDMA network, users are distributed in Mdifferent classes. Furthermore, power level with which users in class j,j = 2⋯M, transmit optical pulses, is twice the power level at which users of class j - 1transmit their optical pulses. We achieve optical transmitter structure that satisfies these conditions using power control schemes. Also, we suggest two receiver structures for the aforementioned multiclass multilevel system. The first and simple receiver structure... 

A low power four bit mixed Successive Approximation Register (SAR)-Flash Analog to Digital Converter (ADC) for Sigma-Delta ADC applications is presented. The ADC uses three comparators in order to reduce the latency of typical SAR ADCs. Three comparators are used for conversion of 2 bits per one clock cycle. One of the Digital to Analog Converters (DACs) is replaced by three resistors which can save power and area. The ADC is simulated by Cadence Spectre using TSMC 0.18um COMS technology. The power consumption at 165MS/s and 1.8V supply voltage is 1.8mW. The SNDR and SFDR for 10MHz input are 19.8dB and 28.4dB, respectively  

Wound-Rotor (WR) resolvers are similar to two-phase synchronous generators. Their difference is related to the excitation signal. While DC voltage is used for exciting synchronous generator, high frequency AC voltage is employed for that of resolver. The common waveform for excitation signal of resolver is sinusoidal voltage. However, preparing the high frequency sinusoidal voltage in the resolver to digital converter (RDC) is always a challenge. Therefore, in this paper different high frequency AC waveforms are applied as the excitation signal of the resolver and the estimated position, resulted from RDC, is discussed. The aim of this work is to find an appropriate excitation waveform that... 

This paper presents actual cases of steady reactive power oscillation of distributed generations (DGs) during parallel operation with the main grid. The cause of the problem was found to be the adverse effects of excitation system voltage regulation. It is shown, through preliminary investigation and detailed simulation studies, that how the excitation control system can be modified to overcome this problem. On-site test results verify the analysis results and effectiveness of the remedial actions. Finally, general practical recommendations are offered for excitation control of synchronous generator-based DG, such that it performs properly, both in grid connected and in islanding conditions  

A problem associated with modeling and control of the power factor correction rectifiers is that the ac variations in duty cycle, as well as in the ac input voltage and current are not small, and hence the traditional small signal analysis is not justified. Nonetheless, the low-frequency components of the converter can be modeled via the circuit averaging technique, but the resulting equivalent circuits are, in general, time varying and highly nonlinear. Nonlinear stability analysis methods are not appropriate for analysis and control design of such complicated circuits. In this paper a piecewise affine approximation is introduced for modeling of switching circuits. This approach makes the...