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Voltage-frequency planning for thermal-aware, low-power design of regular 3-D NoCs
, Article Proceedings of the IEEE International Conference on VLSI Design ; 2010 , p. 57-62 ; ISSN: 10639667 ; ISBN: 9780769539287 ; Sarbazi-Azad, H ; Sharif University of Technology
Abstract
Network-on-Chip combined with Globally Asynchronous Locally Synchronous paradigm is a promising architecture for easy IP integration and utilization with multiple voltage levels. For power reduction, multiple voltage-frequency levels are successfully applied to 2-D NoCs, but never with a generic approach to 3-D counterparts; in which low heat conductivity of insulator layers makes high dense temperature distribution at layers away from heat sink. In this paper, a thermal-aware methodology for regular 3-D NoCs based on multiple voltage levels is proposed. Given an application task graph, this methodology determines an efficient mapping of tasks onto network tiles, considering inherent...
Voltage-frequency planning for thermal-aware, low-power design of regular 3-D NoCs
, Article Proceedings of the IEEE International Conference on VLSI Design, 3 January 2010 through 7 January 2010, Bangalore ; 2010 , Pages 57-62 ; 10639667 (ISSN) ; 9780769539287 (ISBN) ; Sarbazi Azad, H ; Sharif University of Technology
2010
Abstract
Network-on-Chip combined with Globally Asynchronous Locally Synchronous paradigm is a promising architecture for easy IP integration and utilization with multiple voltage levels. For power reduction, multiple voltage-frequency levels are successfully applied to 2-D NoCs, but never with a generic approach to 3-D counterparts; in which low heat conductivity of insulator layers makes high dense temperature distribution at layers away from heat sink. In this paper, a thermal-aware methodology for regular 3-D NoCs based on multiple voltage levels is proposed. Given an application task graph, this methodology determines an efficient mapping of tasks onto network tiles, considering inherent...