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frequency-synthesizers
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A multi-band frequency synthesizer for DVB-H
, Article International Review of Electrical Engineering ; Volume 4, Issue 5 , 2009 , Pages 1110-1116 ; 18276660 (ISSN) ; Atarodi, M ; Sharif University of Technology
2009
Abstract
A fully integrated multi-band frequency synthesizer for Inphase and Quadrature local oscillator signal generation in Digital Video Broadcasting to Handheld receivers is presented. In the proposed PLL-based integer-N synthesizer, all of the allocated frequencies for DVB tuners, in VHF, UHF and L bands, are generated. Two voltage controlled oscillators cover a frequency range of 1880-3632 MHz by using switched-capacitor banks. The VCO frequency is divided by 2, 4 and 16 to generate the quadrature signals at the synthesizer output. A fast adaptive frequency calibration block selects the closest VCO frequency to the target frequency by setting the capacitor bank control code prior to the start...
A non-linear neural D/A converter for direct digital frequency synthesizers
, Article International Joint Conference on Neural Networks 2006, IJCNN '06, Vancouver, BC, 16 July 2006 through 21 July 2006 ; 2006 , Pages 2669-2672 ; 10987576 (ISSN); 0780394909 (ISBN); 9780780394902 (ISBN) ; Sedighi, B ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2006
Abstract
In this paper, a new non-linear D/A converter (DAC) is presented. This D/A converter uses neural network to approximate a sine function. It is targeted for direct digital frequency synthesizers in which the phase to sine amplitude conversion is usually performed using a ROM. Utilizing the proposed DAC, the power hungry ROM is removed. A design example is presented and the performance of the DAC is compared to the conventional method. The impact of non-idealities on the performance of the system is also investigated. © 2006 IEEE
Novel frequency synthesizer for spur level reduction
, Article 27th Iranian Conference on Electrical Engineering, ICEE 2019, 30 April 2019 through 2 May 2019 ; 2019 , Pages 76-81 ; 9781728115085 (ISBN) ; Ghajari, S ; Safarian, A ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2019
Abstract
A novel frequency synthesizer architecture for reducing spur level is presented. By using a feedforward path a new zero in the transfer function is generated which enables us to increase the capacitor tied to the control voltage line and thus reducing spur level. A fast settling technique is also used to compensate the effect of spur reduction technique on settling time. Different blocks of frequency synthesizer are implemented in MATLAB/Simulink. Simulations show 13 dB improvement in reference spur level compared to conventional architecture for a 2.4 GHz frequency synthesizer
A novel low power architecture for DLL-based frequency synthesizers
, Article Circuits, Systems, and Signal Processing ; Volume 32, Issue 2 , 2013 , Pages 781-801 ; 0278081X (ISSN) ; Sharif University of Technology
2013
Abstract
This paper presents a novel DLL-based frequency synthesizer architecture to generate fractional multiples of reference frequency and reduce the power consumption of the frequency synthesis block. The architecture is adopted for French VHF application as an example. The DLL architecture allows for minimal area, while consuming low power. The proposed circuit can operate at a substantially low supply voltage. The circuit level and system level designs are presented. It was shown that for the mentioned standard, a mere 27 delay stages for VCDL are sufficient to cover French VHF band. Simulation results confirm the analytical predictions. The proposed DLL-based frequency synthesizer is...
A divide-by-3 frequency divider for I/Q generation in a multi-band frequency synthesizer
, Article APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems, Macao, 30 November 2008 through 3 December 2008 ; 2008 , Pages 1383-1386 ; 9781424423422 (ISBN) ; Atarodi, M ; Sharif Bakhtiar, M ; Sharif University of Technology
2008
Abstract
A divide-by-3 frequency divider for Inphase and Quadrature (I/Q) LO signal generation in a multi-band frequency synthesizer is presented. Using divisor numbers other than powers of 2 (2n) for quadrature signal generation, reduces the required frequency range of the VCO in multi-band frequency synthesizers. The divide-by-3 circuit is designed in a 0.18um CMOS technology. © 2008 IEEE
A 5 GHz, 1.5 Volt and very low-power cmos frequency synthesizer for wireless communications
, Article 2002 45th Midwest Symposium on Circuits and Systems, Tulsa, OK, 4 August 2002 through 7 August 2002 ; Volume 3 , 2002 , Pages III536-III539 ; Sharif University of Technology
2002
Abstract
A 5GHz, 1.5 Volt and low power CMOS frequency synthesizer with LC-tuned VCO (voltage controlled oscillator) is presented. The synthesizer consists of an LC-tuned VCO, an injection-lock frequency divider, a very low power prescaler which brings 2.5GHz range frequency to 11 MHz, a phase-frequency detector and charge-pump with improved architecture. Spiral inductors with Q-factor of 9 are used for the LC-tuned 5 GHz VCO. A fixed 2 frequency divider based on injection-locking phenomenon is used to bring 5 GHz VCO frequency to 2.5GHz. Both VCO and injection-locked divider's oscillators are tuned with NMOS varactors with their bodies are grounded, resulting in about 700 MHz tuning range....
Design of Low Spur Fast Settling Integer-N Frequency Synthesizer for Bluetooth Application
, M.Sc. Thesis Sharif University of Technology ; Safarian, Amin Ghasem (Supervisor) ; Atarodi, Mojtaba (Supervisor)
Abstract
Frequency synthesizers are one of the most critical building blocks of RF systems. Their task is to produce high-frequency precise and stable clock signals from a low-frequency source. The signal used in mixers to up-convert and down-convert desired signals in transceivers and the precise clock of analog to digital converters are made by frequency synthesizers. Designing frequency synthesizer, because of its lots of parameter and dependency of these parameters to each other, is a hard task which forces designers to propose new structures. In this thesis, an integer-N frequency synthesizer for Bluetooth application, with the goals of decreasing spurious tones power and settling time, is...
Design and Implementation of a CMOS Fractional-N Frequency Synthesizer for UHF RFID Readers
,
M.Sc. Thesis
Sharif University of Technology
;
Sharif Bakhtiar, Mehrdad
(Supervisor)
Abstract
A 1.8-v 1.8-GHz fully integrated CMOS fractional-N frequency synthesizer is designed and tested for UHF RFID readers. The synthesizer employs a dual-loop architecture to realize a monolithic design with more optimal trade-off among phase noise, channel spacing, reference frequency and settling time compared to the conventional integer-N phase-locked-loop architecture. Due to the large self-interference and the backscatter scheme of the passive tags, reader synthesizer’s phase noise requirement is stringent to minimize the sensitivity degradation of the reader RX. A 1.8-GHz complementary VCO with noise filter has been used to achieve these tough specifications. Also, since a large KVCO can...
Design and Implementation of Fully Integrated Frequency Synthesizer for Biomedical Applications
, M.Sc. Thesis Sharif University of Technology ; Atarodi, Mojtaba (Supervisor)
Abstract
Fully integrated frequency synthesizer is one of the important system-on-chips building blocks. Among this circuit’s remarkable applications, Bioelectronics field is very common. In these applications, advanced microelectronic circuits are used in order to diagnosis and treatment of diseases. The aim of this thesis is design and implementation a wideband frequency synthesizer in a 0.18um CMOS technology. The main usage of this circuit is in a fully integrated implantable biomedical sensory chip. This circuit generates two necessary local signals in sensory chip to stimulus cells and process the information.
Frequency synthesizer is based on phased locked loop (PLL) circuit and produce...
Frequency synthesizer is based on phased locked loop (PLL) circuit and produce...
Design of a DLL-Based Frequency Synthesizer for Wireless Recievers
,
M.Sc. Thesis
Sharif University of Technology
;
Sharif Khani, Mohammad
(Supervisor)
;
Atarodi, Mojtaba
(Supervisor)
Abstract
A DLL-based frequency synthesizer that has the capability of producing fractional multiples of the reference frequency is designed and implemented in this thesis. The new structures for producing fractional multiples of reference frequency with DLLs are also presented. The designed frequency synthesizer is not a Sigma-delta modulator for synthesizing. This structure has a low jitter and phase-noise, low chip area, low settling time and a good stability due to its DLL-based nature. Also, a systematic model for simulating DLLs in MATLAB Simulink is proposed that is very efficient for giving a better insight to designing of DLLs. The settling time of the proposed topology for DLL is 2.5us. The...
Spur Level Reduction in Direct Digital Synthesizer
, M.Sc. Thesis Sharif University of Technology ; Akbari, Mahmoud (Supervisor) ; Banai, Ali ($item.subfieldsMap.e)
Abstract
Direct digital synthesizers (DDS) are one type of frequency synthesizer that are used for creating arbitrary waveforms from a reference clock with fixed-frequency and have various applications in signal generators, local oscillators in telecommunication systems, mixers, modulators and part of phase-locked loop.Despite of numerous advantages of direct digital synthesizers like high accuracy, fast switching ability, low power consumption and etc, beacuse of some available alternative errors in its structure like phase truncation, Inside band of desired output signal, independent unwanted signals namely spur were created. Spurs creat trouble in the use of sensor or radar systems and limit the...
A wide tuning range, fractional multiplying delay-locked loop topology for frequency hopping applications
, Article Analog Integrated Circuits and Signal Processing ; Volume 46, Issue 3 , 2006 , Pages 203-214 ; 09251030 (ISSN) ; Torkzadeh, P ; Atarodi, M ; Sharif University of Technology
2006
Abstract
This paper introduces a low-jitter and wide tuning range delay-locked loop (DLL) -based fractional clock generator (CG) topology. The proposed fractional multiplying DLL (FMDLL) architecture overcomes some disadvantages of phase-locked loops (PLLs) such as jitter accumulation while maintaining the advantageous of a PLL as a multi-rate fractional frequency multiplier. Based on this topology, a CG with 1-2.5 GHz output frequency tuning range has been designed in a digital 0.18 um CMOS technology while the multiplication ratios are M+k/(2N C ) in which M, k, and N C are adjustable. To generate some finer ratios, k is changed periodically or randomly (by a digital delta-sigma modulator) between...
A reduced complexity 3 rd order digital delta-sigma modulator for fractional-N frequency synthesis
, Article Proceedings - 17th International Conference on VLSI Design, Concurrently with the 3rd International Conference on Embedded Systems Design, Mumbai, 5 January 2004 through 9 January 2004 ; Volume 17 , 2004 , Pages 615-618 ; 10639667 (ISSN) ; Atarodi, S. M ; Bornoosh, B ; Kusha, A. A ; Sharif University of Technology
2004
Abstract
A reduced complexity third-order digital delta-sigma modulator is presented. The modulator consists of two cascaded sections to produce proper shaping of quantization noise with minimum hardware. A new architecture for a digital third-order delta-sigma modulator based on Ritchie structure is proposed. The measurement results show 94dB SNR and 65% dynamic range
Covering VHF frequency band with novel DLL-based frequency synthesizer
, Article 2011 International Conference on Communications and Signal Processing, ICCSP 2011, Kerala, 10 February 2011 through 12 February 2011 ; 2011 , Pages 297-299 ; 9781424497980 (ISBN) ; Sharifkhani, M ; Hashemi, M ; Sharif University of Technology
Abstract
This paper presents a new architecture for a DLL based frequency synthesizer for wireless transceivers. Owing to its DLL based nature, the synthesizer generates the target frequencies with minimum phase noise and jitter. To cover the desired frequency proposed architecture consists of mixer and divider. As an example, VHF frequency band of IRAN is covered. The circuit level design guidelines and power consumption trade-offs are presented. It was shown that for the mentioned standard a 40 delay cell and 9 switches for switching channels is sufficient. Simulation results confirm the analytical predictions
New method to synthesize the frequency bands with DLL-based frequency synthesizer
, Article 2011 International Conference on Communications and Signal Processing, ICCSP 2011, Kerala, 10 February 2011 through 12 February 2011 ; 2011 , Pages 300-304 ; 9781424497980 (ISBN) ; Gholamidoon, M ; Hashemi, M ; Sharif University of Technology
Abstract
This paper presents a new architecture for a DLL based frequency synthesizer. Occupying low area, lower power consumption and phase noise are the advantages of this novel architecture. DLLs are first ordered systems, so good stability can be obtained in this design. This structure also can be used for generating fractional multiple of reference frequencies. The proposed circuit can operate at a substantially low supply voltage. A case in point, the synthesizer is adopted to create the channel frequencies of French DVB-H/T standard. The circuit is designed based on 0.13um CMOS Technology. Also power consumption trade-offs are introduced. It was shown that 27 delay cells are sufficient to...
Modeling of DLL-based frequency multiplier in time and frequency domain with Matlab Simulink
, Article IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, 6 December 2010 through 9 December 2010 ; 2010 , Pages 1051-1054 ; 9781424474561 (ISBN) ; Sharifkhani, M ; Saeedi, S ; Sharif University of Technology
Abstract
A systematic procedure of simulating charge pump based delay locked loops (DLLs) represents in this paper. The presented procedure is based on the systematic modeling of the DLL components in Matlab Simulink simulator. The system has been designed for 1Hz input clock signal that by changing the whole system scale, it can be used for every other input frequencies. The simulation results in Matlab and design considerations for DLL based frequency multiplier are presented
Systematic modeling and simulation of DLL-based frequency multiplier
, Article 2010 11th International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design, SM2ACD 2010, 4 October 2010 through 6 October 2010 ; 2010 ; 9781424468164 (ISBN) ; Sharifkhani, M ; Ebrahimi, A ; Saeedi, S ; Atarodi, M ; Sharif University of Technology
Abstract
This paper represents a systematic procedure of simulating charge pump based delay locked loops (DLLs). The presented procedure is based on the systematic modelling of the DLL components in Matlab simulink simulator. The system has been designed for 1Hz input clock signal that by changing the whole system scale, it can be used for every other input frequencies. The simulation results in Matlab and design considerations for DLL based frequency multiplier are presented
Simulation and improvement of two digital adaptive frequency calibration techniques for fast locking wide-band frequency synthesizers
, Article 2007 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2007, Rabat, 2 September 2007 through 5 September 2007 ; February , 2007 , Pages 136-141 ; 1424412781 (ISBN); 9781424412785 (ISBN) ; Momtazpour, M ; Alizadeh, B ; Sharif University of Technology
2007
Abstract
Fast locking PLL-based wide-band frequency synthesizers used in high performance RF transceivers often require multi-band voltage controlled oscillator (VCO). These types of frequency synthesizers employ both discrete and continuous tuning mechanisms to satisfy wide frequency range and low VCO tuning gain simultaneously. To facilitate discrete tuning mechanisms, an auxiliary digital loop is required in order to select proper band of VCO. This digital loop is called adaptive frequency calibration (AFC). In this paper two methods of previous AFC architectures are discussed and improved to gain the minimum possible lock time of PLL. Then, these two methods are simulated and implemented over...
Design of Low Phase Noise DCO in All Digital Frequency Synthesizers
, M.Sc. Thesis Sharif University of Technology ; Atarodi, Mojtaba (Supervisor)
Abstract
A new class of design has been introduced in the RF circuits and Frequency Synthesizers, which is based on the digital circuits. Implementation of the digital synthesizers suppresses the need to use loop filter and thus reduces the loop lock time. In this thesis different topologies of digitally controlled oscillators using inductor and capacitor tank and all digital architectures used in high frequency all digital synthesizers in 0.18um CMOS technology has been inspected and simulated. Novel techniques introduced to improve the ring oscillator-based design’s specifications which doesn’t need inductor. Using the introduced techniques, the phase noise has been lessened acceptably with respect...
Design, Fabrication and Analysis of Fast Wideband Frequency Synthesizer with Low Spurious and Phase Noise
, M.Sc. Thesis Sharif University of Technology ; Banayi, Ali (Supervisor)
Abstract
In this thesis, design and fabrication of wide band frequency synthesizer with low spurious and low phase noise is investigted. It is very important to use an apropriate frequency synthesizer structure which would meet intended properties. In order to reach a low step size and high switching speed, using DDS is recomended; as well as using composition of DDS and PLL in order to meet a low spurious level. The main objective of this thesis is to investigate the best composition of outlet spures; so beside optimization of other properties, the main motivation has been focused on decreasing spures. Moreover, after studying Mechanisms of spures production in DDS outlet, some methods for...