Sharif Digital Repository

The continued migration to smaller nanometer geometries brought fundamental limits to traditional on-chip hard wires performance. According to the International Technology Roadmap for Semiconductor (ITRS), feature size shrinking leads an increase in the operating frequency of RFCMOS devices. Thus, new interconnect methodologies such as radio frequency (RF) wireless can be employed on future chips projected for intra-chip wireless data communications. The size of Si integrated antenna in these frequencies will be several millimetres and the antenna length will be decrease by frequency increasing. In this paper, we have proposed an optimum radiation pattern achieved by a phased array (PA)... 

This paper introduces a Dynamic Read SRAM (DRSRAM) architecture for high-density subthreshold RAM applications. DRSRAM performs a dynamic read operation to overcome the poor stability and bitline leakage problem of 6T SRAM cell in sub-threshold region. It is shown that there is fundamental limit for wordline activation time and recovery time under a given cell mismatch and bitline leakage. To verify the proposed technique, a 64128 bit array of the 6T bit-cell is simulated in 90 nm CMOS technology. The simulation results show a 100% noise margin enhancement at subthreshold region. This design operates down to 300 mV at a 1 MHz clock rate with noise margins as large as 72 mV. This design...