Search for: gain-errors
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    Analysis and design of a DC to 18 GHz 6-bit attenuator with simultaneous phase and gain error correction

    , Article AEU - International Journal of Electronics and Communications ; Volume 110 , 2019 ; 14348411 (ISSN) Ahmadikia, A ; Karami, P ; Atarodi, S. M ; Sharif University of Technology
    Elsevier GmbH  2019
    In this paper the design of a digital step attenuator with simultaneous low phase and gain error characteristics is investigated. First, the loading effect of the consecutive blocks of an N-bit attenuator on the precision of the attenuation levels is analyzed. Then a modified structure to decrease the loading effect as well as the phase error of the attenuator blocks is presented. A comprehensive analysis of the circuit is performed and some design guidelines have described. Finally, a 6-bit attenuator with attenuation range of 0.5–31.5 dB and resolution of 0.5 dB is implemented in 0.18 µm complementary metal–oxide-semiconductor (CMOS) technology. The root mean square (RMS) gain error and... 

    Elimination of the effect of bottom-plate capacitors in C-2C DAC using a layout technique

    , Article Microelectronics Journal ; Volume 46, Issue 12 , 2015 , Pages 1275-1282 ; 00262692 (ISSN) Khorami, A ; Sharifkhani, M ; Sharif University of Technology
    An efficient layout technique is proposed to eliminate the effect of the bottom-plate capacitors in a C-2C Digital to Analog Converter (DAC). Using this technique, the bottom-plate capacitors of 2C capacitors in the C-2C structure are placed in parallel with 1C capacitors. Then, the effect of the bottom plate capacitors is nulled by modifying the size of the main 1C capacitors. Hence, avoiding the complexity of calibration, this technique can preclude the effect of the bottom-plate to ground capacitance. Statistical simulations prove that the proposed technique is robust to non-ideal effects such as mismatch or parasitic capacitors. A 10-bit C-2C DAC is modeled in COMSOL Multiphysics using... 

    A fully integrated 0.18-μm CMOS transceiver chip for X-band phased-array systems

    , Article IEEE Transactions on Microwave Theory and Techniques ; Volume 60, Issue 7 , 2012 , Pages 2192-2202 ; 00189480 (ISSN) Gharibdoust, K ; Mousavi, N ; Kalantari, M ; Moezzi, M ; Medi, A ; Sharif University of Technology
    An X-band core chip is designed and fabricated in 0.18-μm CMOS technology, which can significantly reduce the monolithic microwave integrated circuit count required for realizing an active beam-former T/R module. The core chip consists of two RX/TX paths, each of which includes a 6-b phase shifter, a 6-b attenuator, along with two input and output amplifiers. A new architecture for realizing such a core chip system and a low loss circuit for 5.625° phase shift block are proposed. The overall rms phase and gain errors are better than 2° and 0.25 dB, respectively, in both RX/TX paths. The gain of each path is around 12 dB, while the output 1-dB compression point is higher than 10 dBm over the... 

    INL prediction method in pipeline ADCs

    , Article APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems, 4 December 2006 through 6 December 2006 ; 2006 , Pages 13-16 ; 1424403871 (ISBN); 9781424403875 (ISBN) Nikandish, G ; Sedighi, B ; Bakhtiar, M. S ; Sharif University of Technology
    In this paper a general method for system level prediction of INL in pipeline analog to digital converters is presented. For each stage of the ADC, a new error model consisting of an input referred gain error and a nonlinear term is introduced. An analytic method to calculate INL from all error sources is presented. INL model for a switched-capacitor implementation is also presented. ©2006 IEEE  

    A full 360° vector-sum phase shifter with very low rms phase error over a wide bandwidth

    , Article IEEE Transactions on Microwave Theory and Techniques ; Volume 60, Issue 6 PART 1 , 2012 , Pages 1626-1634 ; 00189480 (ISSN) Asoodeh, A ; Atarodi, M ; Sharif University of Technology
    An innovative vector-sum phase shifter with a full 360° variable phase-shift range in 0.18-μm CMOS technology is proposed and experimentally demonstrated in this paper. It employs an I/Q network with high I/Q accuracy over a wide bandwidth to generate two quadrature basis vector differential signals. The fabricated chip operates in the 2.3-4.8 GHz range. The root-mean-square gain error and phase error are less than 1.1 dB and 1.4° over the measured frequency span, respectively. The total current consumption is 10.6 mA (phase shifter core: ∼2.6 mA) from a 1.8 V supply voltage and overall chip size is 0.87 × 0.75 mm 2. To the best of the authors' knowledge, this circuit is the first... 

    Analysis of random capacitor mismatch errors in pipeline analog-to-digital converters

    , Article Proceedings - IEEE International Symposium on Circuits and Systems ; 2011 , Pages 514-517 ; 02714310 (ISSN) ; 9781424494736 (ISBN) Nikandish, G ; Medi, A ; Sharif University of Technology
    A new modeling and analysis of the nonlinearities caused by the capacitor mismatch errors in the pipeline analog-to-digital converters (ADCs) is presented. Error in each stage is modeled by an input-referred gain error and a nonlinear term. A method is proposed for calculation of the ADC integral nonlinearity (INL) from the total input referred error. Analytical expressions for estimation of the ADC INL in terms of standard deviation of random capacitor mismatch errors are derived. The proposed model is verified by system-level Monte Carlo simulations