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hamming-codes
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Multiple upsets tolerance in SRAM memory
, Article 2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007, New Orleans, LA, 27 May 2007 through 30 May 2007 ; 2007 , Pages 365-368 ; 02714310 (ISSN) ; Zarandi, H. R ; Pradhan, D. K ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2007
Abstract
This paper presents a high level method called Matrix code to protect SRAM-based memories against multiple bit upsets. The proposed method combines hamming code and parity code to assure the reliability of memory in presence of multiple bit-upsets with low area and performance overhead. The method is evaluated using one million multiple-fault injection experiments; next reliability and MTTF of the protected memories are estimated based on fault injection experiments and several equations. The fault detection/correction coverage are also calculated and compared with previous methods i.e., Reed-Muller and hamming code. The results reveal that the proposed method behaves better than these...
An efficient technique to tolerate MBU faults in register file of embedded processors
, Article CADS 2012 - 16th CSI International Symposium on Computer Architecture and Digital Systems ; 2012 , Pages 115-120 ; 9781467314824 (ISBN) ; Fazeli, M ; Patooghy, A ; Miremadi, S. G ; Sharif University of Technology
2012
Abstract
This paper presents a Data Width-aware Register file Protection (DWRP) technique to cope with Multiple Bit Upsets (MBUs) occurring in the register file of embedded processors. The DWRP technique has been proposed based on the fact that there are often a significant number of bits in the register file, which are not fully occupied by data. The DWRP technique efficiently exploits these available free bits for reliability enhancement purposes. In this regard, every register is equipped with three extra tag bits to specify the amount of available free bits in a register. Then the appropriate parity or hamming code is used based on the information of the tag field to protect the register file...
Design of a Fault Tolerant ARM-Based Processor on FPGA
, M.Sc. Thesis Sharif University of Technology ; Rashidian, Bijan (Supervisor) ; Vosughi Vahdat, Bijan (Supervisor)
Abstract
The charged particles in space strike the silicon surface of an embedded system in a satellite and cause fault occurrence in its operation. So some methods should be employed to reduce the effects of the faults. The methods that are implemented in system level are widely used because of their low cost and high reliability. The processors are responsible for performing main processes in embedded systems. On the other hand, the ARM processors are good choices for utilizing in satellites because of their low size, low power consumption and high performance. Also, FPGAs have made a major improvement in embedded system design. So with implementing ...
A Survey and Practical Comparison of Top Techniques on Fault tolerant CPU Design
, M.Sc. Thesis Sharif University of Technology ; Tabandeh, Mahmoud (Supervisor)
Abstract
Confronting with cosmic rays in electronic parts of space systems, especially in processors and their peripherals, has always been noteworthy topic. By decreasing the aspects of transistors and their voltages, fault occurrence problem in digital integrated circuits not only has been increased in space systems, but also infects on mission critical systems that work at ground level. Since there are many reports about the effect of high energy particles, like neutrons which are present in earth atmosphere, in sub-100 nm digital circuits.In this thesis we are discussing about architecture level techniques for hardening processors against soft errors of radiation.It has been done for each part of...
Investigation and reduction of fault sensitivity in the FlexRay communication controller registers
, Article 27th International Conference on Computer Safety, Reliability, and Security, SAFECOMP 2008, Newcastle upon Tyne, 22 September 2008 through 25 September 2008 ; Volume 5219 LNCS , 2008 , Pages 153-166 ; 03029743 (ISSN); 3540876979 (ISBN); 9783540876977 (ISBN) ; Miremadi, S. G ; Sharif University of Technology
2008
Abstract
It is now widely believed that FlexRay communication protocol will become the de-facto standard for distributed safety-critical automotive systems. In this paper, the fault sensitivity of the FlexRay communication controller registers are investigated using transient single bit-flip fault injection. To do this, a FlexRay bus network, composed of four nodes, was modeled. A total of 135,600 transient single bit-flip faults were injected to all 408 accessible single-bit and multiple-bit registers of the communication controller in one node. The results showed that among all 408 accessible registers, 30 registers were immediately affected by the injected faults. The results also showed that...
A multi-bit error tolerant register file for a high reliable embedded processor
, Article 2011 18th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 22011, 11 December 2011 through 14 December 2011 ; December , 2011 , Pages 532-537 ; 9781457718458 (ISBN) ; Hosseini, M ; Vahdat, B. V ; Rashidian, B ; Sharif University of Technology
2011
Abstract
The vulnerability of microprocessors to soft errors is increasing due to continuous shrinking in fabrication process. Recent studies show that 1-5% of the SEUs (single event upset) can cause MBUs (multiple bit upsets). The probability of MBU generation due to SEU is increasing because of the reduction in minimum energy required to flip a memory bit in modern technologies. Register file is the most sensitive component in a microprocessor. In this paper, we present an innovative way to protect registers in a 64-bit register file for a RISC processor using extended Hamming (8, 4) code (SEC-DED code) and narrow-width values. A narrow-width value can be represented by half number of bits of the...
A Micro-FT-UART for safety-critical SoC-based applications
, Article International Conference on Availability, Reliability and Security, ARES 2009, Fukuoka, Fukuoka Prefecture, 16 March 2009 through 19 March 2009 ; 2009 , Pages 316-321 ; 9780769535647 (ISBN) ; Miremadi, S. G ; Ejlali, A. I ; Sharif University of Technology
2009
Abstract
This paper presents the design of a fault-tolerant universal asynchronous receiver transmitter (UART) called micro-FT-UART for safety-critical SoC-based applications. This UART exploits advantages of three fault-tolerant techniques to tolerate soft errors. The three techniques are triple modular redundancy (TMR), Hamming code and a new technique called correction by parity storing (CPS). An VHDL model of a micro-UART is simulated by the ModelSim v.6.0 and synthesized by the Synopsys Design Compiler v.X-2005.09- SP2. About 1000 single-bit errors and 1000 multiple-bit errors are injected into different parts of the micro-UART to find out the error sensitivity of each specific part. Considering...
A power efficient approach to fault-tolerant register file design
, Article Proceedings of the IEEE International Frequency Control Symposium and Exposition, 4 January 2008 through 8 January 2008, Hyderabad ; 2008 , Pages 21-26 ; 0769530834 (ISBN); 9780769530833 (ISBN) ; Miremadi, S. G ; Fazeli, M ; Sharif University of Technology
2008
Abstract
Recently, the trade-off between power consumption and fault tolerance in embedded processors has been highlighted. This paper proposes an approach to reduce dynamic power of conventional high-level fault-tolerant techniques used in the register file of processors, without affecting the effectiveness of the fault-tolerant techniques. The power reduction is based on the reduction of dynamic power of the unaccessed parts of the register file. This approach is applied to three transient fault-tolerant techniques: Single Error Correction (SEC) hamming code, duplication with parity, and Triple Modular Redundancy (TMR). As a case study, this approach is implemented on the register file of an...