Sharif Digital Repository

End-to-end delay, throughput, energy consumption, and silicon area are the most important design metrics of networks-on-chip (NoCs). Although several analytical models have been previously proposed for predicting such metrics in NoCs, very few of them consider the effect of message waiting time in the buffers of network routers for predicting overall power consumptions and none of them consider structural heterogeneity of network routers. This paper introduces two inter-related analytical models to compute message latency and power consumption of NoCs with arbitrary topology, buffering structure, and routing algorithm. Buffer allocation scheme defines the buffering space for each individual... 

End-to-end delay, throughput, energy consumption, and silicon area are the most important design metrics of networks-on-chip (NoCs). Although several analytical models have been previously proposed for predicting such metrics in NoCs, very few of them consider the effect of message waiting time in the buffers of network routers for predicting overall power consumptions and none of them consider structural heterogeneity of network routers. This paper introduces two inter-related analytical models to compute message latency and power consumption of NoCs with arbitrary topology, buffering structure, and routing algorithm. Buffer allocation scheme defines the buffering space for each individual... 

During the past decade, elliptic curve cryptography (ECC) has been widely deployed in different scenarios as the main asymmetric cryptosystem due to its smaller key length and relatively higher speed compared with other asymmetric cryptosystems. The most critical operation in ECC computation is point multiplication. In some popular applications such as signature verification schemes, the double point multiplication can be exploited. In this paper, we propose an algorithm and its corresponding architecture to speed up the double point multiplication using a modified binary differential addition chain. The proposed method is highly parallelizable and has been implemented on Virtex-4, Virtex-5,... 

Reliability and low power consumption are two major design objectives in today's embedded systems. Since floating-point units (FPU) are required for some embedded applications (e.g., multimedia applications), careful considerations should be given to the reliability and power consumptions of FPUs used in embedded systems. When using existing fault handling mechanisms for FPUs, it has been observed that the division operation imposes a considerable hardware overhead as compared to the addition, subtraction, and multiplication operations. Although the division operation is less frequently used, in reliable applications it is a must that all the components operate properly. In this paper, we... 

Nowadays, handheld devices such as smartphones provide users with multi-touch input screens. Displaying interactive and touch-enabled 3D environments in such handheld devices has become popular in different applications like games or virtual reality. Technologies such as Web3D and WebGL have made the creation and display of 3D environments in mobile devices easier than ever. However, object manipulation techniques are not as well developed. For example, moving an object within the 3D environment or other similar object-specific manipulations are neither intuitive nor easy to perform. Current manipulation techniques like Gizmo that are successful in systems that use mouse and keyboard are not... 

Network-on-Chip (NoC) is a key element in the total power consumption of a chip multiprocessor. Dynamic Voltage Scaling is a promising method for power saving in NoCs since it contributes to reduction in both static and dynamic power consumptions. In this paper, we propose a novel scheme to reduce on-chip network power consumption when the number of Virtual Channels (VCs) with active allocation requests per cycle is less than the number of total VCs. In our method, we introduce a reconfigurable arbitration logic which can be configured to have multiple latencies and hence, multiple slack times. The increased slack times are then used to reduce the supply voltage of the routers in order to... 

The reliable transfer in Network on Chips (NoCs) can be threatened by crosstalk fault occurring in wires. Crossstalk fault is due to inter-wire coupling capacitance that based on the patterns of transitions appearing on the wires, significantly limits the reliability of NoCs. Among these transitions, 101 and 010 bit patterns impose the worst crosstalk effects to wires. This work intends to increase the reliability of NoCs against crosstalk faults by applying an improved Fibonacci-based numeral system, called Doubled-Penultimate Fibonacci (DP-Fibo). In the DP-Fibo coding algorithm, code words without ‘101’ and ‘010’ bit patterns are produced to reduce crosstalk faults. Experimental results... 

We consider a DVS-enabled single-processor firm real-time (FRT) system with Poisson arrival jobs having exponential execution times and generally distributed relative deadlines. The queue size of the system bounds the number of jobs which may be available therein. Further, the processor speed depends on the number of jobs in the system which varies because of the job arrivals, service completions, and dead-line misses. Thus, the processor power consumption, includling both the dynamic and leakage powers, depends on the stochastic nature of the system. More specifically, the instantaneous dynamic power consumption lonely depends on the number of jobs at that moment. However, the instantaneous... 

There are many sites specially designed for mobile phones. In cases such as the registering in websites, some hackers write programs to make automatic false enrolments which waste the resources of the website. Therefore, it is necessary to distinguish between human users and computer programs. These systems are known as CAPTCHA (Completely Automated Public Turing test to tell Computers and Human Apart). CAPTCHA methods are mainly based on the weak points of OCR (Optical Character Recognition) systems while using them difficult in tools such as PDAs (Personal Digital Assistant) or mobile phones that lack a big keyboard. So the Non-OCR-Based CAPTCHA methods are proposed which are do not need...