Sharif Digital Repository

Some of the recent approaches regarding leverage PCM will be reviewed in this chapter. The chapter starts with a discussion regarding future main memory systems that includes hybrid architecture schemes using both PCM and DRAM arrays. Later, we focus on PCM only approaches and this section will help describe some techniques for reducing the increased read latency because of slow writes in PCMs. In this chapter, we also illustrate wear-leveling approaches and review the security problems of this memory approach which are lifetime limited. This section includes an overview of the recent security aware wear-leveling techniques, whose methods help detect attacks, and their issues during the... 

Emerging non-volatile memories (NVMs) are notable candidates for replacing traditional DRAMs. Although NVMs are scalable, dissipate lower power, and do not require refreshes, they face new challenges including shorter lifetime and security issues. Efforts toward securing the NVMs against probe attacks pose a serious downside in terms of lifetime. Cryptography algorithms increase the information density of data blocks and consequently handicap the existing lifetime enhancement solutions like Flip-N-Write. In this paper, based on the insight that compression can relax the constraints of lifetime-security trade-off, we propose CryptoComp, an architecture that, taking the advantage of block size... 

Limited endurance problem and low cell reliability are main challenges of phase change memory (PCM) as an alternative to DRAM. To further prolong the lifetime of a PCM device, there exist a number of techniques that can be grouped in two categories: 1) reducing the write rate to PCM cells, and 2) handling cell failures when faults occur. Our experiments confirm that during write operations, an extensive non-uniformity in bit ips is exhibited. To reduce this non-uniformity, we present byte-level shifting scheme (BLESS) which reduces write pressure over hot cells of blocks. Additionally, this shifting mechanism can be used for error recovery purpose by using the MLC capability of PCM and... 

In this chapter, we first introduce one shifting mechanisms in order to further prolonging the lifetime of a phase change memory (PCM) device, reducing the write rate to PCM cells, and handling cell failures when hard faults occur. In this line, Byte-level Shifting Scheme (BLESS) is addressed and reduces write pressure over hot cells of blocks. Additionally, we illustrate that using the MLC capability of PCM and manipulating the data block to recover faulty cells can also be used for error recovery purpose. Next, we propose another intra-line level pairing scheme (ILP). This novel recovery mechanism can statically partition a data block into a small number of groups and efficiently benefits... 

To address the problem of fast degradation in PCM main memory systems in the presence of severe cell wear-out, this chapter introduces and evaluates some ways to deal with hard error issues in phase change memory. Our observation reveals when some memory pages reach their endurance limits, other pages may be far from their limits even when using a perfect wear-leveling. Recent studies have proposed redirection or correction schemes to alleviate this problem, but all suffer from poor throughput or latency. In this chapter, we also propose On-demand page paired PCM (OD3P) memory system. Our technique mitigates the problem of fast failure of pages by redirecting them onto other healthy pages,...