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    Behavioral-level hardware trust: analysis and enhancement

    , Article Microprocessors and Microsystems ; Volume 58 , 2018 , Pages 24-33 ; 01419331 (ISSN) Farajipour Ghohroud, N ; Hessabi, S ; Sharif University of Technology
    Elsevier B.V  2018
    Abstract
    Hardware IPs are mostly presented in Register Transfer Level (RTL) description. Although considerable attention has been paid to hardware Trojan detection and design-for-trust at gate level and lower levels, so far there have been few methods at RT Level and behavioral RTL. We propose an approach to analyze circuit susceptibility to Trojan at the behavioral level, based on controllability analysis. We propose three design-for-trust methods, which reduce circuit vulnerability to hardware Trojans by increasing the probability of Trojan detection. We use side-channel Trojan detection method based on power consumption to evaluate Trojan detection probability. Our proposed methods can improve... 

    Code layout optimization for Near-Ideal instruction cache

    , Article IEEE Computer Architecture Letters ; Volume 18, Issue 2 , 2019 , Pages 124-127 ; 15566056 (ISSN) Ansari, A ; Lotfi Kamran, P ; Sarbazi Azad, H ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2019
    Abstract
    Instruction cache misses are a significant source of performance degradation in server workloads because of their large instruction footprints and complex control flow. Due to the importance of reducing the number of instruction cache misses, there has been a myriad of proposals for hardware instruction prefetchers in the past two decades. While effectual, state-of-the-art hardware instruction prefetchers either impose considerable storage overhead or require significant changes in the frontend of a processor. Unlike hardware instruction prefetchers, code-layout optimization techniques profile a program and then reorder the code layout of the program to increase spatial locality, and hence,... 

    Investigation and reduction of fault sensitivity in the FlexRay communication controller registers

    , Article 27th International Conference on Computer Safety, Reliability, and Security, SAFECOMP 2008, Newcastle upon Tyne, 22 September 2008 through 25 September 2008 ; Volume 5219 LNCS , 2008 , Pages 153-166 ; 03029743 (ISSN); 3540876979 (ISBN); 9783540876977 (ISBN) Sedaghat, Y ; Miremadi, S. G ; Sharif University of Technology
    2008
    Abstract
    It is now widely believed that FlexRay communication protocol will become the de-facto standard for distributed safety-critical automotive systems. In this paper, the fault sensitivity of the FlexRay communication controller registers are investigated using transient single bit-flip fault injection. To do this, a FlexRay bus network, composed of four nodes, was modeled. A total of 135,600 transient single bit-flip faults were injected to all 408 accessible single-bit and multiple-bit registers of the communication controller in one node. The results showed that among all 408 accessible registers, 30 registers were immediately affected by the injected faults. The results also showed that... 

    Evaluation of some exponential random number generators implemented by FPGA

    , Article IASTED International Conference on Parallel and Distributed Computing and Networks, as part of the 23rd IASTED International Multi-Conference on Applied Informatics, Innsbruck, 15 February 2005 through 17 February 2005 ; 2005 , Pages 578-583 ; 10272666 (ISSN) Timarchi, S ; Miremadi, S. G ; Ejlali, A. R ; Fahringer T ; Hamza M. H ; Sharif University of Technology
    2005
    Abstract
    Normally, random number generators produce uniformly distributed values. In some cases, such as Monte Carlo simulation, non-uniform distributed values (e.g. exponential distribution and weibull distribution) are required. One way of producing non-uniformly distributed random values, is to add an extra hardware to a uniformly distributed random number generator. In this paper, three different methods are studied to generate exponential random values. These methods are based oft three algorithm of logarithm evaluating namely: CORDIC, Interpolation and Piecewise lookup table. The study is based on an experimental evaluation of the above methods, using FPGA chips, to compare the speed, hardware... 

    Digital multiplierless realization of a calcium-based plasticity model

    , Article IEEE Transactions on Circuits and Systems II: Express Briefs ; Volume 64, Issue 7 , 2017 , Pages 832-836 ; 15497747 (ISSN) Jokar, E ; Soleimani, H ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2017
    Abstract
    Calcium is a highly widespread and versatile intracellular ion that can control a wide range of temporal dynamics in the brain such as synaptic plasticity. This brief presents a novel and efficient digital circuit for implementing a calcium-based plasticity model aimed at reproducing relevant biological dynamics. Accordingly, we investigate the feasibility of the proposed model in a minimal neural network stressing on the effect of calcium oscillations on synaptic plasticity with various neuronal stimulation protocols. MATLAB simulations and physical implementations on field-programmable gate array confirm that the proposed model, with considerably low hardware overhead, can fairly mimic the... 

    Digital implementation of a biological astrocyte model and its application

    , Article IEEE Transactions on Neural Networks and Learning Systems ; Volume 26, Issue 1 , 2014 , Pages 127-139 ; 2162237X (ISSN) Soleimani, H ; Bavandpour, M ; Ahmadi, A ; Abbott, D ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2014
    Abstract
    This paper presents a modified astrocyte model that allows a convenient digital implementation. This model is aimed at reproducing relevant biological astrocyte behaviors, which provide appropriate feedback control in regulating neuronal activities in the central nervous system. Accordingly, we investigate the feasibility of a digital implementation for a single astrocyte and a biological neuronal network model constructed by connecting two limit-cycle Hopf oscillators to an implementation of the proposed astrocyte model using oscillator-astrocyte interactions with weak coupling. Hardware synthesis, physical implementation on field-programmable gate array, and theoretical analysis confirm...