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hardware-software-co-design
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Hardware/Software Codesign of Network Router Inspired by Software-Defined Network
, M.Sc. Thesis Sharif University of Technology ; Jahangir, Amir Hossein (Supervisor)
Abstract
There is a plethora of research and implementations that intend to increase the performance and reduce implementation costs of network routers. In this work, we review previous designs and propose a new network router design that is based on software-defined networks. Our design separates the data plane and the control plane from each other and connects both parts by using OpenFlow protocol. The control plane consists of a general small computer that utilizes the Quagga software to enforce the routing protocols. The control plane translates routing decisions to OpenFlow instructions and sends them to the data plane. The data plane is based on a switch that supports the OpenFlow protocol...
A polynomial algorithm for partitioning problems
, Article Transactions on Embedded Computing Systems ; Volume 9, Issue 4 , 2010 ; 15399087 (ISSN) ; Jahangir, A. H ; Sharif University of Technology
2010
Abstract
This article takes a theoretical approach to focus on the algorithmic properties of hardware/software partitioning. It proposes a method with polynomial complexity to find the global optimum of an NP-hard model partitioning problem for 75% of occurrences under some practical conditions. The global optimum is approached with a lower bound distance for the remaining 25%. Furthermore, this approach ensures finding the 2-approximate of the global optimum partition in 97% of instances where technical assumptions exist. The strategy is based on intelligently changing the parameters of the polynomial model of the partitioning problem to force it to produce (or approach) the exact solution to the...
Using on-chip networks to implement polymorphism in the co-design of object-oriented embedded systems
, Article Journal of Computer and System Sciences ; Volume 73, Issue 8 , December , 2007 , Pages 1221-1231 ; 00220000 (ISSN) ; Mohammadzadeh, N ; Hessabi, S ; Sharif University of Technology
2007
Abstract
The Network-on-Chip (NoC) paradigm brings networks inside chips. We use the routing capabilities inside NoC to serve as a replacement for Virtual Method Table (VMT) for Object-Oriented (OO) designed hardware/software co-design systems where some methods could be implemented as hardware modules. This eliminates VMT area and performance overhead in OO co-designed embedded systems where resources are limited and where some functionality needs to be implemented in hardware to meet performance goals of the system. Our experimental results on real world embedded applications show up to 32.15% lower area and up to 5.1% higher speed compared to traditional implementation using VMT. © 2007 Elsevier...
The ODYSSEY approach to early simulation-based equivalence checking at ESL level using automatically generated executable transaction-level model
, Article Microprocessors and Microsystems ; Volume 32, Issue 7 , 2008 , Pages 364-374 ; 01419331 (ISSN) ; Hessabi, S ; MohammadZadeh, N ; Zainolabedini, N ; Sharif University of Technology
2008
Abstract
Design technology is expected to rise to electronic system-level (ESL). This necessitates new techniques and tools for synthesizing ESL designs and for verifying them before and after ESL synthesis. A promising verification strategy for future very complex designs is to initially verify the design at the highest level of abstraction, and then check the equivalence of the lower level automatically generated models against that initial golden model. We present one such approach to simulation-based functional verification implemented in our ESL design methodology called ODYSSEY. Our ESL synthesis tool generates a transaction-level model (TLM) at TLM level 2 (i.e., design with partial timing)...