Sharif Digital Repository

Taylor Expansion Diagram (TED) has been recently introduced as a compact and canonical representation for arithmetic functions with finite Taylor series. It can represent Boolean logic interacting with arithmetic functions canonically. One of the main disadvantages of TED is that relations must be bit expanded to be represented in TED. This paper represents a method for high-level symbolic simulation and property checking based on integer equations. Functionality of design is represented in Conditional TED (CTED), which is our enhancement of TED to represent relations without bit expansion. This way, a more compact structure is achieved for high-level designs, containing control path... 

This paper presents a method for functional verification of HDL models of digital circuits. The method is based on a co-operation between a simulator and an emulator and utilizes the advantages of both simulation-based and emulation-based verification to form a fast co-verification approach. This is done by verifying the intensive time-consuming part of the circuit in the emulator and the non-synthesizable part as well as the part of the circuit that needs intensive redesign process during the early steps of the design phase in the simulator. To demonstrate the co-verification approach, a tool was developed, which supports Verilog, VHDL, and mixed Verilog-VHDL models. Three benchmarks...