Sharif Digital Repository

In this paper, two output matching networks (OMNs) are proposed for integrated class-J and class-J-1 mode power amplifiers (PAs). The first MN provides the required load impedances of the class-J mode (i.e., Z(f0) = Ropt + j Ropt and Z(2 f0) = -j (3π/8)Ropt), where as the second MN realizes the optimal impedances of class-J-1 PAs (i.e., Z(f0) = Ropt - j Ropt and Z(2 f0) = j (3π/8)Ropt ). Detailed theoretical analyses are presented for each MN, and the values of matching components (i.e., inductors and capacitors) are obtained in terms of Ropt. Analytical derivations are verified by simulation results, while bandwidth and loss performances of each MN are also characterized. Two... 

Recently, class-J₂ operation mode has been proposed in the literature for high-efficiency power amplifier (PA) design. It has been shown that the output power (Pout) of a class-J₂ PA can be 1.5 dB higher than Pout of a class-J counterpart, whereas the theoretical drain efficiency of the class-J₂ mode can be as high as 83%. This paper is devoted to introduce and characterize the class-J₂₃ mode of operation, which is the generalized form of the class-J₂ mode and provides a new design space to realize highly efficient PSs. In this new PA mode, the third-harmonic voltage is also included in the drain voltage of the transistor to increase the drain efficiency up to 95.4% in theory. Design space... 

This paper presents the theoretical introduction and experimental validation of the "Class-J2 Mode Power Amplifier," which provides higher efficiency and output power compared with conventional class-J mode counterpart. This mode of operation is realized by injection of the second-harmonic current to drain node of a class-J power amplifier (PA) to reduce the 45° phase shift between drain current and voltage signals. Similar to class-J PAs, the second-harmonic impedance of class-J2 PAs is purely reactive to simplify the design of the output matching network. The auxiliary second-harmonic injection circuit comprises a transistor biased in class-B mode followed by a class-C biased amplifier to... 

Recently, class-J₂ operation mode has been proposed in the literature for high-efficiency power amplifier (PA) design. It has been shown that the output power (Pout) of a class-J₂ PA can be 1.5 dB higher than Pout of a class-J counterpart, whereas the theoretical drain efficiency of the class-J₂ mode can be as high as 83%. This paper is devoted to introduce and characterize the class-J₂₃ mode of operation, which is the generalized form of the class-J₂ mode and provides a new design space to realize highly efficient PSs. In this new PA mode, the third-harmonic voltage is also included in the drain voltage of the transistor to increase the drain efficiency up to 95.4% in theory. Design space... 

In this paper, the performance of the class-J mode power amplifier (PA) is studied when an auxiliary network performs active load modulation on the main transistor. Load modulation is realized by injecting an additional class-C like current with conduction angle of $alpha $ to the drain node of the main transistor. The injected current employs a phase shift of $phi $ with respect to the half-sinusoidal current of the main transistor, and its maximum value is tuned with the size of the transistor used in the auxiliary network. Detailed theoretical formulations are presented for the optimal load impedances of the PA at the fundamental and second-harmonic frequencies. Furthermore, the output... 

In this article, a design methodology is presented to realize integrated class-F high-power amplifiers (HPAs). A harmonic-control network (HCN) is proposed to present short- and open-circuit impedances to each transistor employed in the output stage of the HPA at 2f_0 and 3f_0 frequencies. The HCN absorbs the parasitic capacitance of the transistor and lends itself to be absorbed in the matching and power combiner networks, reducing the die area of the HPA. A proof-of-concept 9.7-10.3-GHz class-F HPA was designed and implemented in a 0.25-μm GaAs pHEMT technology with VDD of 6 V. The designed HPA consists of two amplifying stages, and its output stage includes 16 transistors in parallel to...