Sharif Digital Repository

Graphics Processing Units (GPUs) employ large register files to accommodate all active threads and accelerate context switching. Unfortunately, register files are a scalability bottleneck for future GPUs due to long access latency, high power consumption, and large silicon area provisioning. Prior work proposes hierarchical register file to reduce the register file power consumption by caching registers in a smaller register file cache. Unfortunately, this approach does not improve register access latency due to the low hit rate in the register file cache. In this article, we propose the Latency-Tolerant Register File (LTRF) architecture to achieve low latency in a two-level hierarchical... 

DSP algorithms are one of the most important components of modern embedded computer systems. These applications generally include fixed point and floating-point arithmetic operations and trigonometric functions which have long latencies and high power consumption. Nonetheless, DSP applications enjoy from some interesting characteristics such as tolerating slight loss of accuracy and high degree of value locality which can be exploited to improve their power consumption and performance. In this paper, we present an application-specific result-cache that aims to reduce the power consumption and latency of DSP algorithms by reusing the results of the arithmetic operations executed on the same... 

DSP algorithms are one of the most important components of modern embedded computer systems. These applications generally include fixed point and floating-point arithmetic operations and trigonometric functions which have long latencies and high power consumption. Nonetheless, DSP applications enjoy from some interesting characteristics such as tolerating slight loss of accuracy and high degree of value locality which can be exploited to improve their power consumption and performance. In this paper, we present an application-specific result-cache that aims to reduce the power consumption and latency of DSP algorithms by reusing the results of the arithmetic operations executed on the same... 

With the emergence of Non-Volatile Memories (NVMs) and their shortcomings such as limited endurance and high power consumption in write requests, several studies have suggested hybrid memory architecture employing both Dynamic Random Access Memory (DRAM) and NVM in a memory system. By conducting a comprehensive experiments, we have observed that such studies lack to consider very important aspects of hybrid memories including the effect of: a) data migrations on performance, b) data migrations on power, and c) the granularity of data migration. This paper presents an efficient data migration scheme at the Operating System level in a hybrid DRAM-NVM memory architecture. In the proposed... 

Triple Modular Redundancy (TMR) is a historical and long-time-used approach for masking various kinds of faults. By employing redundancy and analyzing the results of three separate executions of the same program, TMR is able to attain excellent levels of reliability. While TMR provides a desirable level of reliability, it suffers from the high power consumption of the redundant hardware, a severe detriment to its broad adoption. The energy consumption of TMR can be mitigated if its operations are divided into two stages, and one stage is dropped in the absence of fault. Such an approach, which is evaluated in recent research, however, quickly fails in the presence of permanent faults, as we... 

Triple Modular Redundancy (TMR) is a historical and long-time-used approach for masking various kinds of faults. By employing redundancy and analyzing the results of three separate executions of the same program, TMR is able to attain excellent levels of reliability. While TMR provides a desirable level of reliability, it suffers from the high power consumption of the redundant hardware, a severe detriment to its broad adoption. The energy consumption of TMR can be mitigated if its operations are divided into two stages, and one stage is dropped in the absence of fault. Such an approach, which is evaluated in recent research, however, quickly fails in the presence of permanent faults, as we... 

Nowadays, embedded processors are widely used in wide range of domains from low-power to safety-critical applications. By providing prominent features such as variant peripheral support and flexibility to partial or major design modifications, field-programmable gate arrays (FPGAs) are commonly used to implement either an entire embedded system or a hardware description language-based processor, known as soft-core processor. FPGA-based designs, however, suffer from high power consumption, large die area, and low performance that hinders common use of soft-core processors in low-power embedded systems. In this paper, we present an efficient reconfigurable architecture to implement soft-core... 

Two main objectives in designing real-time embedded systems are high reliability and low power consumption. Hardware replication (e.g., standby-sparing) can provide high reliability while keeping the power consumption under control. In this paper, we consider a standby-sparing system where the main tasks on primary cores are scheduled by our proposed peak-power-aware earliest-deadline-first policy while the backup tasks on spare cores are scheduled by our proposed peak-power-aware earliest-deadline-late policy to meet the chip thermal design power (TDP) constraint. These policies provide the best opportunity to shift the task executions as much as possible to minimize execution overlaps...